S4. Plasma Science and Etching Technology

Low Damage/Pulsing/Cycling



Date: Thursday, February 5, 2015

Time: 13:00-17:00

Room: #307, Conference Room (South), COEX

Language: English

Simultaneous interpretation will NOT be provided.


Registration Fee                                                                                       

 SEMI Member  Non-Member  Student
 Pre-regi(by Jan 23)  120,000 won  150,000 won  60,000 won
 Onsite  150,000 won  180,000 won  80,000 won


Plasma technology applied to plasma assisted deposition and etching is becoming more critical in the semiconductor device fabrication as the critical dimension of the semiconductor device sizes is less than ten nanometer scale. As feature sizes continue to shrink and new device architectures are introduced, controlling process variability in manufacturing becomes much more challenging. Looking ahead to next-generation requirements, feature dimensions will soon have tolerances that are on the order of a few atoms. At the same time, device aspect ratios continue to increase, and topographies are becoming even more complicated. For the most advanced structures, conventional plasma etch and deposition processes are unable to meet these requirements, and new approaches are needed. ALE and ALD provide a solution by using cycles of multi-step processes that deposit or remove a few atomic layers at a time, thereby delivering precise control. The challenge is to deliver sufficient productivity to make these processes suitable for increasingly cost-sensitive manufacturing environments.




Sponsored by






Jaesoung Kim(Dongbu HiTek)

Gyoungjin Min(Samsung Electronics)

Jong Won Shon(ASM Genitech Korea)

Geun Young Yeom(Sungkyunkwan University)

IC Jang(Lam Research Korea)

Taewoo Jung(SK hynix)






Perspective in High Aspect Ratio Etcher: How to Overcome the Limits?

Injun Kim, SEMES




Advances in RF Power Delivery for Critical Plasma Etch Processes

Prof. Steven Shannon, North Carolina State University (invited)




The Bias Pulsing Effect on the Si Etching Process at Narrow Pattern

Keun Hee Bai, Samsung Electronics (invited)







Modeling of Plasma-induced Damage in Advanced Transistors in ULSI Circuits

Prof. Koji Eriguchi, Kyoto University (invited)




Plasma Etch in the Era of Atomic Scale Fidelity

Thorsten Lill, Lam Research




High Selectivity Etch Technologies for Sub-10nm Devices

Amulya Athayde, Applied Materials








Plasma Monitoring and End Point Detection

Prof. Heeyeop Chae, Sungkyunkwan University (invited)




High Aspect Ratio Contact (HARC) Etch Technology for 3D NAND Flash Memory

JaeSung Yoon, SK hynix




Development of Plasma Informatioin Based Virtual Metrology (PI-VM) for Plasma-assisted Etch and Deposition Processes

Seolhye Park, Seoul National University 



*The agenda will be subject to change without notice.