PROGRAMS

 

The SEMI Technology Symposium (STS) 2016, which held in conjunction with SEMICON Korea 2016 provides a dynamic spectrum of technology direction for semiconductor manufacturing in the next generation from a wide variety of aspects. The symposium will cover the latest technologies topics: Advanced Lithography, Interconnection & Advanced Process, Device, Plasma Science and Etching, Contamination-free Manufacturing and CMP Technology, and Electropackage System and Interconnect Product.

 

STS focuses specifically on suggesting semiconductor industry’s future and recent technology trends. Your participation will enhance the value of STS and provide with valuable contents to semiconductor industry people.

 

SEMI welcomes industry input and suggestions from potential speakers. SEMI is soliciting technical papers related to any of the following topics;

 

 


S1. Advanced Lithography

  • - Resist Processes and Materials
  • - Photomask Processes and Materials
  • - Lithography Simulation (Wafer/Mask Processes),OPC and Design for Manufacturing
  • - Multiple Exposure and Double Patterning Techniques
  • - Advanced Metrology Technology for Wafer and Mask
  • - Extreme Ultraviolet Lithography
  • - Directed Self Assembly
  • - Alternative Lithography (Nano-Imprint and others)
  • - Application of Lithography to Nanotechnology

 

S2. Advanced Process Technology: Dielectrics, Metals, and Other Materials 

  • - Advanced Gapfill Technology
  • - Interconnection (Interconnect/Barrier Metal , Gate Electrode, Salicidation, Optical 
  •   Interconnection)
  • - Dielectric (high k, low k, Gate Dielectric, Ferroelectric, Passivation)
  • - Doping  & Heat Treatment Process  (I2p, Plasma Doping, GILD, SADS, RTP, Furnace, 
  •   Damage Control)
  • - Epitaxial Growth (Blanket, Selective, Device Integration)
  • - SOI Materials & Processes (Wafer Manufacturing, Device Manufacturing)
  • - Materials and Process for Non Volatile Memory Devices (PCRAM, STT-RAM, ReRAM, 
  •   PoRAM, etc)
  • - Nano Process Technology (Quantum Dot/Nanowire/Layer Formation)
  • - 2D Materials (Graphene, Sulfide, and etc.)

 

S3. Device Technology

  • - SoC Technology
  • - Advanced CMOS Technology
  • - Advanced Memory Technology
  • - SOI Devices
  • - RF Devices
  • - Nano-scale Devices
  • - Thin Film Devices
  • - Interconnection Technology
  • - Advanced Junction/Doping Technology
  • - Process/Device/Interconnection Modeling
  • - Device/Interconnection Reliability
  • - Organic Devices (OLED/Organic TFT)
  • - Advanced Display Device Technology
  • - Device Technology for Mobile/ Automotive Application

 

S4. Plasma Science and Etching Technology

  • - Patterning Etch Technologies related to DPT, QPT, DSA, EUV and New Material/Structure
  • - Selective Etch Technique
  • - Atomic layer etching (ALE) and Low Damage Etching (LDE)
  • - Etch Technologies related to FEOL (FiNFET Gate etc.) and BEOL (SAC, Low-k etc.)
  • - HARC & HART Etch Technology
  • - TSV and 3-D Etch Technology
  • - New & Novel Material Etch for MRAM, ReRAM, and etc.
  • - New Plasma Tools and New Unit Technologies 
  •   (Pulsing, Fast MFC, Low-temp chiller, TMP, etc.)
  • - Tool to Tool Matching (TTTM) Technologies
  • - Plasma & Process Diagnostics, sensors, and control
  • - Simulation and Modeling for Plasma source and process

 

S5. Contamination-Free Manufacturing and CMP Technology

  • - Advanced Wet/Dry Surface Preparation in FEOL/BEOL
  • - Micro-, Nano-contamination Control
  • - Damage/Loss Free Nano Particle Removal
  • - Yield Enhancement Technology
  • - Environmentally Benign Manufacturing/PFC Emission Reduction
  • - Advanced Wet/ Dry Cleaning for 3D Structure and New Materials
  • - Advances in CMP, Related Processes and Equipment
  • - CMP Consumables and Metrology
  • - Scratch Reduction/Mechanism
  • - CMP Modeling and Simulation
  • - Post CMP Cleaning

 

S6. Electropackage System and Interconnect Product

  • - Packaging in 5G Mobile Technology
  • - EMI Shielding Technology
  • - Antenna Technology for High Speed Mobile Application
  • - Memory Stack Technology for High Bandwidth Memory
  • - Packaging Technology for 64 bit Era
  • - Package-On-Package Technology
  • - Packaging Technology for Speedy Network including Si Photonics
  • - Packaging Technology for Implantable and Wearable Devices


  • Submit an Abstract

    To submit and abstract for consideration, click STS 2016 Call for Papers

    Due date for submission is September 30, 2015. You will be notified status of your submission by October 31, 2015. 

     

    Guidelines

    - Submit a 500 word abstracts and a 100 word biography

    - Accuracy in Title and Description: The quality of the description of your paper matters. It’d be hard to make it through the review process if your paper is focusing on promotion of your company. Focusing on technology is recommended.

    Important Dates

    Abstracts Due

    September 30

    Author Notification

    October 31

    Speaker Letter of Agreement Due

    November 30

    Paper/ PowerPoint Presentation Due

    December 31

    Presentation

    Depending on the session, January 27 or 28, 2016

     

    Contact Us

    JoAnn Lee (julee@semi.org, +82.2.531.7806)