Call for Papers


The SEMI Technology Symposium (STS) 2017, held in conjunction with SEMICON Korea 2017, will provide a dynamic agenda of sessions and presentations on a wide variety of topics in the area of next-generation semiconductor manufacturing. Topics covered include: Advanced Lithography, Interconnection & Advanced Process, Device, Plasma Science and Etching, Contamination-free Manufacturing and CMP Technology, and Electropackage System and Interconnect Product.

STS focuses specifically on exploring current and future trends in semiconductor design and manufacturing. By participating as a presenter, you will enhance the value of the STS and provide valuable information to your peers and other attending industry professionals.

SEMI welcomes input and suggestions for potential speakers. Additionally, SEMI is soliciting technical papers related to any of the following topics:


S1. Advanced Lithography

  • Resist Processes and Materials
  • Photomask Processes and Materials
  • Design Process Technology Co-Optimization for Manufacturability
  • Various Multiple Patterning Techniques
  • Advanced Metrology Technology for Wafer and Mask
  • Extreme Ultraviolet Lithography
  • Directed Self Assembly
  • Alternative Lithography (Nano-Imprint and others)
  • Application of Lithography to Nanotechnology


S2. Advanced Process Technology: Dielectrics, Metals, and Other Materials 

    • Advanced Gapfill Technology
    • Interconnection (Interconnect/Barrier Metal, Gate Electrode, Salicidation, Optical Interconnection)
    • Dielectric (high k, low k, Gate Dielectric, Ferroelectric, Passivation)
    • Doping & Heat Treatment Process (I2p, Plasma Doping, GILD, SADS, RTP, Furnace, Damage Control)
    • Epitaxial Growth (Blanket, Selective, Device Integration)
    • SOI Materials & Processes (Wafer Manufacturing, Device Manufacturing)
    • Materials and Process for Non Volatile Memory Devices (PCRAM, STT-RAM, ReRAM, 3D-NAND, 3D X-point)
    • Nano Process Technology (Quantum Dot/Nanowire/Layer Formation)
    • 2D Materials (Graphene, Sulfide, and etc.)
    • Materials and Process for Beyond Moore


    S3. Device Technology

      • A.I.-friendly Device Technology
      • SoC Technology
      • Advanced CMOS Technology
      • Advanced Memory Technology
      • SOI Devices
      • RF Devices
      • Nano-scale Devices
      • Thin Film Devices
      • Interconnection Technology
      • Advanced Junction/Doping Technology
      • Process/Device/Interconnection Modeling
      • Device/Interconnection Reliability
      • Device Technology for Mobile/ Automotive Application


        S4. Plasma Science and Etching Technology

          • 3D Etch Technologies for VNAND, 3D X-point, FinFET, Nano Wire, TSV and etc.
          • New & Novel Material Etch for MRAM, PRAM, ReRAM, and etc.
          • Patterning Etch Technologies related to DPT, QPT, DSA, EUV and etc.
          • Selective Etch Technique
          • Atomic Layer Etching (ALE) and Low Damage Etching (LDE)
          • Etch Technologies related to FEOL (FiNFET Gate etc.) and BEOL (SAC, Low-k etc.)
          • HARC & HART Etch Technology
          • New Plasma Tools and New Unit Technologies (Pulsing, Fast MFC, Low-temp chiller, TMP, etc.)
          • Tool to Tool Matching (TTTM) Technologies
          • Plasma & Process Diagnostics, Sensors, and Control
          • Simulation and Modeling for Plasma Source and Process 
          • Innovative Approaches to Atomic Layer Material Removal


          S5. Contamination-Free Manufacturing and CMP Technology

            • Advanced Wet/Dry Surface Preparation in FEOL/BEOL
            • Micro-, Nano-contamination Control
            • Damage/Loss Free Nano Particle Removal
            • Yield Enhancement Technology
            • Environmentally Benign Manufacturing/PFC Emission Reduction
            • Advanced Wet/ Dry Cleaning for 3D Structure and New Materials
            • Advances in CMP, Related Processes and Equipments
            • CMP Consumables and Metrology
            • Scratch Reduction/Mechanism
            • CMP Modeling and Simulation 
            • Post CMP Cleaning


              S6. Electropackage System and Interconnect Product

              • Advanced Wafer Level Fan-out Technology 
              • Ultra Thin PoP Technology Using Advanced Wafer Level Fan-out
              • Wafer Warpage Control Technology
              • Memory Stack Technology, Package-on-FoWLP (WLFO) Technology
              • Multi-chip-integration in FoWLP (WLFO)
              • Board Level Reliability with FoWLP (WLFO)
              • Small 3D Form Factor SiP
              • RF MEMS WLP Solution
              • PLP (Panel Level Package) Technology
              • Wafer Molding Technology
              • Wafer Supporting Technology



              Submit an Abstract
              The due date for submission was September 30, 2016. You were notified status of your submission by October 31, 2016.



              • Submit a 500 word abstract and a 100 word biography
              • Accuracy in Title and Description: The quality of the description of your paper matters. Focus on technology challenges and solutions avoiding excessive commercialization of company-specific products or services. Overly commercial presentations will be removed from consideration.


              Important Dates

              Abstracts Due
              September 30
              Author Notification
              October 31
              Speaker Letter of Agreement Due
              November 30
              Paper/ PowerPoint Presentation Due
              December 31
              February 8 or 9, 2017




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