Call for Presentations


The SEMI Technology Symposium (STS) 2018, held in conjunction with SEMICON Korea 2018, will provide a dynamic agenda of sessions and presentations on a wide variety of topics in the area of next-generation semiconductor manufacturing. Topics covered include: Advanced Lithography, Interconnection & Advanced Process, Device, Plasma Science and Etching, Contamination-free Manufacturing and CMP Technology, and Electropackage System and Interconnect Product.

STS focuses specifically on exploring current and future trends in semiconductor design and manufacturing. By participating as a presenter, you will enhance the value of the STS and provide valuable information to your peers and other attending industry professionals.

SEMI welcomes input and suggestions for potential speakers. Additionally, SEMI is soliciting technical papers related to any of the following topics:


S1. Advanced Lithography

  • Resist Processes and Materials
  • Mask Process, Blank, and Infrastructure
  • OPC and Design Process Technology Co-Optimization for Manufacturability
  • Various Multiple Patterning Techniques
  • Advanced Metrology Technology for Wafer and Mask
  • Extreme Ultraviolet Lithography
  • Directed Self Assembly
  • Alternative Lithography (Nano-Imprint and others)
  • Application of Lithography to Nanotechnology
  • High-NA EUV
  • Modeling and Simulation(Resist Stochastic, Mask 3D Effect, and others)
  • Source (LPP, DPP, Free Electron Laser, and others)
  • Device Patterning (Memory, Logic, and others)


S2. Advanced Process Technology: Dielectrics, Metals, and Other Materials 

    • Advanced Gapfill Technology
    • Interconnection (Interconnect/Barrier Metal, Gate Electrode, Salicidation, Optical Interconnection)
    • Dielectric (high k, low k, Gate Dielectric, Ferroelectric, Passivation)
    • Doping & Heat Treatment Process (I2p, Plasma Doping, GILD, SADS, RTP, Furnace, Damage Control)
    • Epitaxial Growth (Blanket, Selective, Device Integration)
    • SOI Materials & Processes (Wafer Manufacturing, Device Manufacturing)
    • Materials and Process for Non Volatile Memory Devices (PCRAM, STT-RAM, ReRAM, 3D-NAND, 3D X-point)
    • Nano Process Technology (Quantum Dot/Nanowire/Layer Formation)
    • 2D Materials (Graphene, Sulfide, and etc.)
    • Materials and Process for Beyond Moore


    S3. Device Technology

      • A.I.-friendly Device Technology
      • SoC Technology
      • Advanced CMOS Technology
      • Advanced Memory Technology
      • SOI Devices
      • RF Devices
      • Nano-scale Devices
      • Thin Film Devices
      • Interconnection Technology
      • Advanced Junction/Doping Technology
      • Process/Device/Interconnection Modeling
      • Device/Interconnection Reliability
      • Device Technology for Mobile/ Automotive Application


        S4. Plasma Science and Etching Technology

          • 3D Etch Technologies for VNAND, 3D X-point, FinFET, Nano Wire, TSV and etc.
          • New & Novel Material Etch for MRAM, PRAM, ReRAM, and etc.
          • Patterning Etch Technologies related to DPT, QPT, DSA, EUV and etc.
          • Selective Etch Technique
          • Atomic Layer Etching (ALE) and Low Damage Etching (LDE)
          • Etch Technologies related to FEOL (FiNFET Gate etc.) and BEOL (SAC, Low-k etc.)
          • HARC & HART Etch Technology
          • New Plasma Tools and New Unit Technologies (Pulsing, Fast MFC, Low-temp chiller, TMP, etc.)
          • Tool to Tool Matching (TTTM) Technologies
          • Plasma & Process Diagnostics, Sensors, and Control
          • Simulation and Modeling for Plasma Source and Process 
          • Innovative Approaches to Atomic Layer Material Removal


          S5. Contamination-Free Manufacturing and CMP Technology

            • Advanced Wet/Dry Surface Preparation in FEOL/BEOL
            • Micro-, Nano-contamination Control
            • Damage/Loss Free Nano Particle Removal
            • Yield Enhancement Technology
            • Environmentally Benign Manufacturing/PFC Emission Reduction
            • Advanced Wet/ Dry Cleaning for 3D Structure and New Materials
            • Advances in CMP, Related Processes and Equipments
            • CMP Consumables and Metrology
            • Scratch Reduction/Mechanism
            • CMP Modeling and Simulation 
            • Post CMP Cleaning


              S6. Electropackage System and Interconnect Product

              • Wire Bonding + Flip Chip
              • Function Die + Embedded Passive Component
              • Top + Bottom Integration
              • Double Side Packaging Integration
              • Different Sensors Integration
              • System-in-Package
              • FOWLP + Conventional Molding Package
              • Thinning Technology
              • Warpage Technology
              • EMI Shielding Technology (for RF, or for RF/ Other Logic Separation)
              • Reliable Cu Interconnection Technology (Cu Bump, Cu Wire)
              • Thermal Management in Package


               Submit abstract 

              (Click here)


              Prospective authors are requested to submit an abstract of 500 words and a 100 words biography by September 30, 2017 indicating the category for which the abstract is being submitted. All abstract must appear on company letterhead, which should include complete address, telephone, fax numbers and e-mail address.

              Presentations are to be non-commercial in that they will focus on the technical merits rather than on individual company’s product benefits. Selected speakers will be notified by October 31, 2017.

              A presentation file will be required to submit by January 19, 2018.

              Accepted presentations are subject to co-copyright with SEMI, who reserves the right to republish, re-sell and display submitted material in whole or in part.


              #4205 Trade Tower
              511 Yeongdong-daero, Kangnam-gu
              Seoul 06164 Korea
              Phone: 82.2.531.7806, Fax: 82.2.551.3406
              For more information: www.semiconkorea.org



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