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Programs Catalog

Programs Catalog

SMART

Here are the programs where you can meet the experts! Mark your calendars!

Keynote Speech

  • Date: Wednesday, January 31
  • Time: 10:00-13:00 
  • Room: #401, COEX

S3. Device Technology

  • Date: Wednesday, January 31
  • Time: 13:00-17:00
  • Room: #317, COEX

S6. Electropackage System and Interconnect Product

  • Date: Thursday, February 1
  • Time: 13:00-17:00
  • Room: #317, COEX

Test Forum

  • Date: Wednesday, January 31
  • Time: 13:00-17:00
  • Room: #318, COEX

SMART Automotive Forum

  • Date: Wednesday, January 31
  • Time: 14:00-17:30
  • Room: #402, COEX

Market Serminar

  • Date: Thursday, February 1
  • Time: 10:00-13:00
  • Room: #318, COEX

Contact 

 

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Standards Room 305, COEX Thursday, February 01
2:00pm to 5:00pm
Reception Grand Ballroom, 5F, Grand InterContinental Seoul Parnas Wednesday, January 31
5:30pm to 8:00pm

Join more than 400 international participants including leaders and executives from industry, academia, and government in this celebration of our industry and SEMICON Korea. Engage customers, peers, and important decision-makers at this exclusive networking event.

Contact

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Standards Room: #305, Conference Room (South), COEX Friday, February 02
10:00am to 12:00pm

1.0    Welcome / Call to Order

  • 1.1    Introductions
  • 1.2    Meeting Reminders (Membership Requirement, Antitrust and Intellectual Property Reminders, Effective Meeting Guidelines)
  • 1.3    Agenda Review

2.0    Review and Approval of Previous Meeting Minutes

3.0    Liaison Report

  • 3.1    Japan chapter of I&C Technical Committee
  • 3.2    North America chapter of I&C Technical Committee
  • 3.3    Taiwan chapter of I&C Technical Committee

4.0    Staff Report

5.0    Ballot Review

  • 5.1    5832 (New Standard, Specification for Generic Counter Model)

6.0    Subcommittee & Task Force Reports

  • 6.1    GEM300 TF
  • 6.2    DDA TF
  • 6.3    ABFI TF  

7.0    Old Business  

  • 7.1   Previous Action Item Review

8.0    New Business

9.0    Action Item Review

10.0  Next Meeting and Adjournment

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Keynotes, SMART Hall E5/6, COEX Wednesday, January 31
10:00am to 12:00pm

Spearkers and Theme will be announced shortly.

  • Venue: To be confirmed
  • Language: English (Simultaneous interpretation WILL be provided) 
  • Registration: Free (Pre-registration is required and Seating is limited)
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Market Room: #318, Conference Room (South), COEX Thursday, February 01
10:00am to 1:00pm

Market Seminar

Language: English (Simultaneous interpretation will NOT be provided)

Registration Fee

  SEMI Member Non-Member Student
Pre-regi(by Feb 1) 120,000 won 150,000 won 60,000 won
Onsite 150,000 won 180,000 won 80,000 won

Register

Most popular issue in semiconductor industry- China, Advanced Packaging, and sub system market will be presented. Also, this seminar will provide the latest outlook for the semiconductor equipment and materials market.

Who Should Attend

  • Senior Professionals in Marketing
  • Sales
  • Procurement
  • Business Development
  • Consulting and Product Planning
  • Finance

Chair

Su Hee Yoo (LG Siltron)

Agenda

13:00-13:40 The Future of FO-WLP
  E. Jan Vardaman, TechSearch International
   
13:40-14:20 Critical Subsystem and Components: Outlook for 2017
  John West, VLSI Research
   
14:20-15:00 Fab Investment and The Surge of China
  Clark Tseng, SEMI
   
15:00-15:40 Semiconductor Equipment and Materials Trends and Outlook
  Dan Tracy, SEMI

*The agenda will be subject to change without notice.

*Presentation materials only for agreed by speaker will be distributed via website after the events.

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Technology Room: #402, Conference Room (South), COEX Thursday, February 01
10:00am to 5:00pm

MI Strategies for 1+3

Language: English and Korean (Simultaneous interpretation will NOT be provided)

Registration Fee

  SEMI Member Non-Member Student
Pre-regi(by Feb 1) 120,000 won 150,000 won 60,000 won
Onsite 150,000 won 180,000 won 80,000 won

Register

We are heading to 1-digit Design Rule for semiconductor industry and it is expected that there are a lot of difficulties we are going to meet in near future. And there has been another approach for developing semiconductor device, which is 3D types of device. In fact, in MI forum, both topics were touched already. However, these hot topics should be revisited for better understanding and MI preparation for both. We believe these two topics are worthy of attention again in 2017 at MI forum. This year, MI forum’s catchphrase is “MI strategies for 1+3” and in here 1 means 1 digit (below 10nm) and 3 does 3D structure. This forum is remarkable one which is only one in all SEMICON shows with 9-years history. We hope you can find needs and solutions of MI for 1+3 with excellent speakers who are invited from the worldwide.

Byoung-Ho Lee, Ph. D. (Research Fellow, SK hynix)

Committee

  • Chang Woo Kim (KLA-Tencor Korea)
  • Harris Kim (Rudolph Technologies Korea)
  • SuYong Park (Semilab Korea)
  • Youngjoon Park (Nanometrics Korea)
  • Chris Park (Nextin)
  • Byoung-Ho Lee (SK hynix)
  • Suk Woo Martin Lee (Applied Materials Korea)
  • Hyung-Yup Lee (Thermo-Fisher MSD Korea)

Agenda

Session 1: Sub 10nm
   
10:00-10:40
Defect Inspection for Advanced Process Nodes
  Kale Beckwitt, Intel (invited)
   
10:40-11:10 Using New Optical Metrology for Inline Electrical Characterization of Advanced Logic Devices
  Andrei V. Shchegrov, KLA-Tencor
   
11:10-11:40 Exploring Multi-patterning Metrology Challenges
  Shimon Levi, Applied Materials
   
11:40-12:10 Recent Advances in Electrical and Optical Characterization Techniques for Advanced Process Control
  Nicolas Laurent, SEMILAB
   
12:10-13:30 Lunch (Lunch Box will be served)
  Sponsored by Applied Materials
   
Session 2: 3D
   
13:30-14:10 Characterization and Metrology from FinFETS & Interconnect to Beyond CMOS Materials
  Prof. Alain C. Diebold, SUNY Polytechnic Institute
  (It's replaced by video recording)
   
14:10-14:50 In-line Metrology and Defectivity for 3D-SOC Hybrid Bonding and TSV Middle Formation
  Maarten Liebens, imec (invited)
   
14:50-15:20 Process Coverage Challenges and Opportunities in Optical CD (OCD) Metrology
  Yudong Hao, Nanometrics
   
15:20-15:40 Break
   
15:40-16:10 Litho CD Metrology for Advanced Multi-Patterning Nodes: A New Optical Solution
  Andrei V. Shchegrov, KLA-Tencor
   
16:10-16:40 Automated Workflow for Process Control and Defect Analysis
  Ozan Ugurlu, Thermo Fisher Scientific (Legacy FEI)
   
16:40-17:10 In-line Metrology for 3D Structure of Semiconductor Devices
  Byoung-Ho Lee, SK hynix

*The agenda will be subject to change without notice. 

*Presentation materials only for agreed by speaker will be distributed via website after the events.

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Reception Room #402, COEX Thursday, February 01
5:00pm to 6:00pm

MI Reception is a special event for MI industry to build the global networking through supply chain and to get together for business opportunities. More than 200 people including MI Forum attendees, speakers and MI Committee members are expected to attend.

 

Contact

 

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Reception Hall E5/6, 3F, COEX Thursday, February 08
10:00am to 10:10am
STS Room: #307, Conference Room (South), COEX Thursday, February 01
9:00am to 12:00pm

Plasma & Etching Tutorial

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Wednesday, January 31
12:30pm to 6:00pm

Admission to the exclusive networking events is availiable for only invitees in advance. If you have any questions, please contact us. 

 

Presidents Reception

  • Date: Wednesday, Jan 31, 2018
  • Time: 17:30 - 20:00
  • Venue: To be confirmed 

VIP Luncheon

  • Date: Wednesday, Jan 31, 2018
  • Time: 12:30 - 13:30
  • Venue: To be confirmed

MI Reception

  • Date: Thursday, February 1, 2018
  • Time: 17:00 - 18:00
  • Venue: #402, COEX

Contact 

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STS Room: #307, Conference Room (South), COEX Wednesday, January 31
1:00pm to 5:00pm

Language: English (Simultaneous interpretation will NOT be provided)

Register

Registration Fee

  SEMI Member Non-Member Student
Pre-regi(by Feb 1) 150,000 won 180,000 won 80,000 won
Onsite 180,000 won 200,000 won 100,000 won

Advanced Lithography session of the STS 2017 will offer the opportunities to review the recent trends in the main stream lithography technologies under the theme of "Readiness of EUV or Alternative".

As EUV is expected to enter the manufacturing phase in near future, it will be a perfect opportunity to check the overall readiness and progress of EUV technology in practical aspects. Prominent leading researchers in the industry will present the up-to-date progress and readiness of EUV technology in each area of expertise, which include resist, mask, OPC, scanner, track, and wafer process integration. Remaining critical issues will be assessed also accordingly. Though EUV gets the upper hand nowadays, still other technologies are very active and show good progress. Therefore, this session will cover the update of the latest progress on alternative technologies such as nano imprint, directed self-assembly and computational lithography as well.

Committee

  • Shangwon Kim (Dongbu HiTek)
  • Seong-Sue Kim (Samsung Electronics)
  • Jaehyun Kim (Dongjin Semichem)
  • Hong Seok Kim (Toppan Photomasks Korea)
  • Chang-Nam Ahn (ASML Korea)
  • Hye-Keun Oh (Hanyang University)
  • Changmoon Lim (SK hynix)
  • Jaesung Choi (ASML Korea)

* The agenda will be subject to change without notice.

* Presentation materials only for agreed by speaker will be distributed via website after the events.

View Full Agenda
STS Room: #308, Conference Room (South), COEX Wednesday, January 31
1:00pm to 5:10pm

Language: English (Simultaneous interpretation will NOT be provided)

Registration Fee

  SEMI Member Non-Member Student
Pre-regi(by Feb 1) 150,000 won 180,000 won 80,000 won
Onsite 180,000 won 200,000 won 100,000 won

Register

In this session, we will be able to share the most up-to-date research and development results in the field of advanced Dielectrics, Metals and Other Materials which are the key enablers of the future semiconductor devices. Many prominent authors from the academia and industries will cover various functional materials research area and semiconductor future memories not only in the view point of fundamental but also for the mass production. Especially, topics regarding material innovation for PcRAM and ReRAM will be highlighted and technical challenges for STT-MRAM mass production will be discussed. Excellent 8 presentations including 4 outstanding invited talks will be given and will cover the major technical issues and the leading edge solutions.

Committee

  • Si Bum Kim (MagnaChip Semiconductor)
  • Hyoungyoon Kim (Dongbu HiTek)
  • Jae Sung Roh (Yonsei University)
  • Kiseon Park (SK hynix)
  • Hyun Chul Sohn (Yonsei University)
  • Gill Lee (Applied Materials)
  • Marco Lee (Lam Research Korea)
  • Jong Min Lee (Eugene Technology)
  • In Gon Lim (DIT)
  • HanJin Lim (Samsung Electronics)
  • Ji Hyun Choi (Tokyo Electron Korea)

*The agenda will be subject to change without notice.

*Presentation materials only for agreed by speaker will be distributed via website after the events.

View Full Agenda
STS Room: #317, Conference Room (South), COEX Wednesday, January 31
1:00pm to 5:00pm

Language: English (Simultaneous interpretation will NOT be provided)

Registration Fee

  SEMI Member Non-Member Student
Pre-regi(by Feb 1) 150,000 won 180,000 won 80,000 won
Onsite 180,000 won 200,000 won 100,000 won

Register

Scaling down issue is still going on in semiconductor technology and it aims to be under 10nm and even beyond. In this process development, a lot of obstacles are waiting for us and needs brand-new approach to find a solution. In this year, we will bring up the challenges toward 10nm and beyond and discuss it with expertise from all of the world. You will find the clue for more than Moore era and all the breakthrough device technology trend, as well.

Committee

  • Oh-Kyong Kwon (Hanyang University)
  • Dong-Won Kim (Samsung Electronics)
  • Tae Kyun Kim (SK hynix)
  • Nae-In Lee (Samsung Electronics)
  • Sang Gi Lee (Dongbu HiTek)
  • Hi-Deok Lee (Chungnam National University)
  • Min Gyu Lim (MagnaChip Semiconductor)
  • Byung Jin Cho (KAIST)
  • Sung Woo Hwang (Samsung Advanced Institute of Technology)

Agenda

13:00-13:40 Story about Single Digit Nodes; Blessing or Curse, You Can Choose
  Youseok Suh, Qualcomm (invited)
   
13:40-14:10 Computational Material Screening: Towards Advanced Semiconductor Devices
  Jai Kwang Shin, Samsung Advanced Institute of Technology
   
14:10-14:50 Novel Transistors by Damage-free Doping Method and Microwave Annealing for Sub-7nm Node
  Yao-Jen Lee, National Nano Device Laboratories (invited)
   
14:50-15:10 Break
   
15:10-15:50 Many-Body Physics Based Devices for Beyond CMOS
  Prof. Leonard Franklin Register, University of Texas at Austin (invited)
   
15:50-16:20 Overcoming the Limitation of Cell Transistor Reliability in Ultimately Scaled DRAM Beyond 20-nm
  Seung Wan Ryu, SK hynix
   
16:20-17:00 Graphene-based Layer Transfer & Crystalline-based ReRAM
  Prof. Jeehwan Kim, MIT (invited)

*The agenda will be subject to change without notice.

*Presentation materials only for agreed by speaker will be distributed via website after the events.

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STS Room: #307, Conference Room (South), COEX Thursday, February 01
1:00pm to 5:00pm

Language: English (Simultaneous interpretation will NOT be provided)

Registration Fee

  SEMI Member Non-Member Student
Pre-regi(by Feb 1) 150,000 won 180,000 won 80,000 won
Onsite 180,000 won 200,000 won 100,000 won

Register

The semiconductor devices have advanced rapidly and changed our world drastically. Do you know there has been the plasma technologies behind these advancements? The plasma technologies have largely contributed to make the sophisticated, complex and various semiconductor devices.

The plasma technologies have created the various process technologies like plasma-assisted etching, deposition and even cleaning and lithography. The plasma studies lead to the high-tech equipment, precious plasma control, software, and simulation in the manufacture environment and also make 3-D structure, fine feature sizes by multi-patterning processing, fine pattern by atomic layer processing, and high performance by metallic materials processing in the application environment.

Above all things, these days we are still focusing on existing devices to maximize the high performance and high productivity. Especially, we are also concentrating on the New Memory Devices featuring high speed, high endurance and low power consumption to gain the variety of applications and functions. To quench the desires, we invited professionals from the industries and academic.

It is believed that this symposium will provide valuable discussion among professionals and experts working in the exciting areas for a long time.

Committee

  • Jaesoung Kim (Dongbu HiTek)
  • Gyoungjin Min (Lam Research Korea)
  • Jongchul Park (Samsung Electronics)
  • Jong Won Shon (ASM Genitech)
  • Geun Young Yeom (Sungkyunkwan University)
  • Minsuk Lee (SK hynix)
  • IC Jang (Lam Research Korea)

Agenda

13:00-13:20 Novel Atomic Order CD Control Technology for 5nm Node and Beyond
  Toru Hisamatsu, Tokyo Electron
   
13:20-13:40 High Aspect Ratio Etch Technology for 3D NAND Devices
  Moosung Kim, SK hynix
   
13:40-14:20 Plasma Etching of Unconventional Materials: Is There Any Systematic Approach?
  Prof. Satoshi Hamaguchi, Osaka University (invited)
   
14:20-14:40 Optimizing Etch Processing for Multi-Patterning 
  Amulya Athayde, Applied Materials
   
14:40-15:00 Break
   
15:00-15:30 Tomographic Emission Spectroscopic Diagnostics of Low Temperature Plasmas
  Prof. Wonho Choe, KAIST (invited)
   
15:30-16:10 Fabrication Challenges of Future 3D Storage Class Memory
  Luca Di Piazza, imec (invited)
   
16:10-16:30 Investigation of Reactive Ion Etching (RIE) Induced Damage Mechanism and Development in Sub-20nm PRAM Patterning
  Hyejin Choi, Samsung Electronics
   
16:30-16:50 Break
   
16:50-17:30 Transition of Memory Technologies
  SangBum Kim, IBM Research (invited)
   
17:30-17:50 How to Tackle One of the Grand Etch Challenges: Uniformity to Zero Edge Exclusion
  Chris GN Lee, Lam Research
   
17:50-18:10 Plasma Dicing - Latest Developments
  Christopher Johnston, Plasma Therm

*The agenda will be subject to change without notice.

*Presentation materials only for agreed by speaker will be distributed via website after the events.

View Full Agenda
STS Room: #308, Conference Room (South), COEX Thursday, February 01
1:00pm to 5:00pm

Language: English (Simultaneous interpretation will NOT be provided)

Registration Fee

  SEMI Member Non-Member Student
Pre-regi(by Feb 1) 150,000 won 180,000 won 80,000 won
Onsite 180,000 won 200,000 won 100,000 won

Register

Co-organized by Korea CMP UGM
Korea Surface Cleaning UGM (KSCUGM)

Continuous shrinkage of device dimension to nm level requires new materials and device structure which demand a new paradigm in contamination control and planarization to improve the production yield and device reliability. CFM technology has become more important in device manufacturing below 20 nm devices. Film loss free and damage free cleaning technology face to serious challenges for next generation device cleaning. Also CMP has grown to be one of the indispensable technologies for advanced node device fabrications such as FinFET, III/V materials and V-NAND. 7-nm logic technology is already under developing now; and CMP will play the main roll on patterning for sub-7 nm technology. In order to achieve the advanced process successfully, it is essential to make the combination among consumable parts in CMP. The purpose of this session is to increase the level of understanding on current and future CFM/CMP technology. Therefore, we are trying to share our intensive and profound perspectives through some remarkable speeches here.

Committee

  • Kyunghyun Kim (Samsung Electronics)
  • Sang Yong Kim (Korea Polytechnics)
  • Ho Youn Kim (Dongbu HiTek)
  • Jin-Goo Park (Hanyang University)
  • Haedo Jeong (Pusan National University)
  • Hong, Chang-Ki (Versum Materials)
  • Eung-Rim Hwang (SK hynix)

Agenda

Session 1: CMP Technology
 
13:00-13:40 Study on CMP Defects Failure Mechanism from the Viewpoint of Cleaner Module Design
  Ji Chul Yang, GLOBALFOUNDRIES (invited)
   
13:40-14:00 Post‐CMP Defect Management in Advanced Node DRAM Development
  Hyo-Chol Koo, SK hynix
   
14:00-14:20 The Necessity of Topology Control CMP in Memory Fabrication
  Hyunsoo-Kim, Samsung Electronics
   
14:20-14:40 New Materials and Impact to CMP for Advanced Node Integration Schemes
  Mark L. O’Neil, Versum Materials 
   
14:40-15:00 Break
   
Session 2: CFM Technology
 
15:00-15:40 Challenges in Wet Processing of High Aspect Ratio Nanostructures
  XiuMei Xu, imec (invited)
   
15:40-16:00 The Prospects and Challenges for Leading Edge Drying Technology
  Ji hoon Cha, Samsung Electronics
   
16:00-16:20 Particle Adsorption Mechanism during Batch Cleaning Process
  Sangsoo Kim, SK hynix
   
16:20-16:40 Continuous Monitoring of Particles at 20nm in Critical Semiconductor Process Chemicals
  Dan Rodier, Particle Measuring Systems

*The agenda will be subject to change without notice.

*Presentation materials only for agreed by speaker will be distributed via website after the events.

View Full Agenda
STS Room: #317, Conference Room (South), COEX Thursday, February 01
1:00pm to 5:00pm

Language: English (Simultaneous interpretation will NOT be provided)

Registration Fee

  SEMI Member Non-Member Student
Pre-regi(by Feb 1) 150,000 won 180,000 won 80,000 won
Onsite 180,000 won 200,000 won 100,000 won

Register

As customers demand for new electronic devices and performance enhancement, high-tech technology is required for package process which was treated as simple manufacturing in the past. In the meantime, advanced wafer-level packaging is attracting attention as a future technology for Internet (IoT) and mobile devices. This is due to its high cost competitiveness compared to existing packaging processes and the ability to package System in packages (SIPs), in which multiple chips and passive components are placed in one package in order to configure the system. In this session, you will find the deep knowledge and opportunities for the recent advances in wafer-level packaging in the market

Committee

  • Gu Sung Kim (Kangnam University)
  • Young Bae Park (Andong National University)
  • Minsuk Suh (SK hynix)
  • WS Shin (ASE Korea)
  • Seh Kwang Lee (Ehwa Diamond)
  • Hanchoon Lee (Dongbu HiTek)
  • Ji Young Chung (Amkor Technology Korea)
  • Soon Jin Cho (Samsung Electro-Mechanics)
  • Taeje Cho (Samsung Electronics)
  • CS Han (ASE Korea)

Agenda

13:00-13:30 Where Is the Destination of the Packaging Technology?
  Choon Heung Lee, Lam Research (invited)
   
13:30-14:00 Market and Technology Trends of Wafer Level Packages
  Santosh Kumar, Yole Developpement
   
14:00-14:40 High Density Package Integration by WLFO based WLSiP and WLPoP
  Steffen Kroehnert, NANIUM (invited)
   
14:40-15:00 Break 
   
15:00-15:20 Study on the Characteristics of Low Temperature Chemical Vapor Deposited Silicon Nitride and Silicon Oxide Film in through Silicon via Bumping Process
  Ju-heon Yang, SK hynix
   
15:20-15:40 Advanced eWLB/FO-WLP (embedded Wafer Level Ball Grid Array/FanOut-Wafer Level Package) for High Frequency Applications
  Seung Wook Yoon, STATS ChipPAC
 
15:40-16:00 A New Wave Fan-Out Package for Heterogeneous Integration
  Walter Jau, ASE
   
16:00-16:20 Break
   
16:20-17:00 Adaptive Patterning for Multi-chip WLFO
  Christopher Scanlan, Deca Technologies (invited)
   
17:00-17:20 Low Temperature Dielectric Material Challenges for 3D Wafer-Level Packaging Applications
  Jinho An, Samsung Electronics
   
17:20-17:40 Silicon-Less Integrated Module (SLIM™) for Mobile Applications
  Wonchul Do, Amkor Technology Korea

*The agenda will be subject to change without notice.

*Presentation materials only for agreed by speaker will be distributed via website after the events.

View Full Agenda
STS COEX Wednesday, January 31
1:00pm to 5:00pm
SMART Wednesday, January 31
2:00pm to 5:00pm

SMART Automotive Forum

  • Date: Wednesday, January 31
  • Time: 14:00 - 17:30
  • Venue: #402, COEX

SMART Manufacturing Forum

  • Date: Thursday, February 1
  • Time: 13:00 - 17:00pm
  • Venue: #301, COEX

 


Contact 

 

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SMART Room #402, COEX Wednesday, January 31
2:00pm to 5:30pm

Smart automotive is driving a new market for semiconductor. Connected car and autonomous driving system needs integrated system, advanced safety features, and infortainment- the value of chips are getting higher than ever in car industry. In a road to smart driving, the challenge of smart automotive is the challenge of semiconductor. As the industry expect to make a fully autonomous car by 2030, the collaboration with semiconductor industry will be essential. This forum will figure out how smart automotive are changing our driving experience and how the semiconductor plays the key role in the new smart world.

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SMART Room: #301, Conference Room (South), COEX Thursday, February 01
1:00pm to 5:00pm

The Key Opportunities and Challenges of the Next Generation of Manufacturing for the Electronics Supply Chain

Language: English and Korean (Simultaneous interpretation will NOT be provided)

Register

Registration Fee

  SEMI Member Non-Member Student
Pre-regi(by Feb 1) 120,000 won 150,000 won 60,000 won
Onsite 150,000 won 180,000 won 80,000 won

In this half-day forum, presenters from over the world will share their insights on the technology drivers and market trends of “Smart Manufacturing” with focus on implications for the semiconductor industry. The continuous advancements of the current automation in semiconductor factory towards a “smart fab of the future” will be a step-by-step transformation model in the upcoming years for global semiconductor industry by providing cases for the successful adoption of more data-driven, optimized manufacturing and new collaboration through the supply chain on issues ranging from interoperability to IP protection.

Who Should Attend
Companies from whole supply chain

Chair

James Amano (SEMI HQ)

Agenda

13:30-14:00 Internet of Things and Large Scale Data Analysis in Intel’s Manufacturing Environment
  Steve Chadwick, Intel
   
14:00-14:30 On the Way to Smart Factory - Driving the Digital Enterprise
  Roland Reuter, Siemens Korea
   
14:30-15:00 Emerging Trends in Semiconductor Manufacturing Analytics and Decision Making
  Kirk Hasserjian, Applied Materials
   
15:00-15:10 Break
   
15:10-15:40 Equipment Engineering Ecosystem for Smart Manufacturing
  Han Joo Lee, SK hynix
   
15:40-16:10 20/20 Vision into Your Manufacturing Plant: Detect, Fix, and Predict
  Tom Ho, BISTel
   
16:10-16:40 Smart Manufacturing & SEMI Standards
  James Amano, SEMI HQ
   
16:40-17:00 Q&A

*The agenda will be subject to change without notice.

*Presentation materials only for agreed by speaker will be distributed via website after the events.

View Full Agenda
Standards

The SEMI Standards Program develops the global standards indispensable in the strengthening of international competitiveness. 

The SEMI Standards Regulations now require that all meeting participants be registered as SEMI Standards Program Members in advance. To become a SEMI Standards Program Member, meeting attendees must register as a Standards Program Member on-line prior to the meeting(s). SEMI Standards Program Membership is available to any interested person without charge and is independent of any other SEMI membership. If you are not yet a Program Member, please register now.

SEMI Standards Membership Application Form


Contact

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Technology Tuesday, January 31
1:00pm to 5:00pm

Technology

View Full Agenda
Technology

 

MI(Metrology and Inspection) Forum 

  • Date: Thursday, February 1
  • Time: 10:00-17:00
  • Room: #402, COEX

 

Test Forum

  • Date: Wednesday, January 31
  • Time: 13:00-17:00
  • Room: #318, COEX

Contact

View Full Agenda
Technology Room: #318, Conference Room (South), COEX Wednesday, January 31
1:00pm to 5:00pm

Extend Horizon of Test Technology

Language: English and Korean (Simultaneous interpretation will NOT be provided)

Registration Fee

  SEMI Member Non-Member Student
Pre-regi(by Feb 1) 120,000 won 150,000 won 60,000 won
Onsite 150,000 won 180,000 won 80,000 won

Register

Committee

  • James JinSoo Ko (Teradyne)
  • Minhyun Kwon (SK hynix)
  • Im Jong Park (Formfactor Korea)
  • Kwonsung Ban (Samsung Electronics)
  • Kyu-hyuk Yeon (ASE Korea)
  • MinHo Chang (Amkor Technology Korea)
  • Jeongho Cho (Advantest Korea)

Agenda

13:00-13:30 New Test Flow Challenges in Semiconductor Test
  Ken Lanier, Teradyne
   
13:30-14:00 5G Cellular and the mmWave Testing Challenge
  Stephen Pruitt, Teradyne
   
14:00-14:30 The Challenges of Testing IoT Modules on ATE Systems
  Jeongseob Kim, Advantest Korea
   
14:30-14:50 Break
   
14:50-16:30 Using OEE Data to Drive Manufacturing Excellence at Test
  Dale Ohmart, Texas Instruments
   
16:30-17:00 Cost of Test Optimization for WLP High Volume QA Testing
  Serge Kuenzli, COHU

*The agenda will be subject to change without notice.

*Presentation materials only for agreed by speaker will be distributed via website after the events.

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Reception Wednesday, January 31
12:30pm to 1:30pm

Contact

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