Programs Catalog

SMART Room 402, COEX Wednesday, January 23

2:00pm to 5:00pm

Date: Jan 23(Wed), 2019
Time: 14:00-17:00
Room: #402, Conference Room (South), COEX
Theme:
Language:

Registration Fee

	SEMI Member	Non-Member	Student
Early Bird (by Jan 24)	180,000 won	200,000 won	100,000 won
Onsite	200,000 won	240,000 won	120,000 won

Agenda

14:00-14:10	Opening

14:10-14:40	Keynote 1: Shaping the Electronic Mobility Experience Berthold Hellenthal, Audi

14:40-15:10	Keynote 2: The Future of Mobility Klaus Meder, Bosch Corporation Japan

15:10-15:40	NVIDIA AI and DRIVE Kazuto Hirose, NVIDIA

15:40-16:00	Break

16:00-16:30	Market Dynamics Driving the Future of Automotive Semiconductors Jim Feldhan, Semico Research

16:30-17:00	Intelligent Semiconductor for Autonomous Driving Jae Hong Choi, Infineon Technologies

17:00-17:30	Safe and Secure Mobility Jooyang Park, NXP Semiconductors

17:30	Adjourn

*The agenda will be subject to change without notice.

* Presentation materials agreed by speaker will be distributed via e-mail after the events.

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Cleaning & CMP Tutorial

Workforce Development Room 308, COEX Thursday, January 24

9:00am to 12:00pm

Date: Jan 24(Thu), 2019
Time: 09:00-12:00
Room: #308, Conference Room (South), COEX
Language:

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EHS Chapter Formation Group Meeting

Standards Room 305, COEX Wednesday, January 23

1:00pm to 3:00pm

Program: EHS Chapter Formation Group Meeting
Date: Jan 23(Wed), 2019
Time: 13:00-15:00
Room: #305, Conference Room (South), COEX

Contact

Standards
Tel: +82-2-531-7808
Mail: eshim@semi.org

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Ferroelectric Tutorial

Workforce Development Room 308, COEX Wednesday, January 23

9:00am to 12:00pm

Date: Jan 23(Wed), 2019
Time: 09:00-12:00
Room: #308, Conference Room (South), COEX
Theme:
Language:
Supported by

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HTU Reunion

Workforce Development Room 301, COEX Friday, January 25

10:00am to 1:00pm

Date: Jan 25(Fri), 2019
Time: 10:00-13:00
Room: #301, Conference Room (South), COEX
Language:

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Industry Leadership Dinner - Invitation Only

Networking Grand Ballroom, 5F, Grand InterContinental Seoul Parnas Wednesday, January 23

5:30pm to 8:00pm

Join more than 400 international participants including leaders and executives from industry, academia, and government in this celebration of our industry and SEMICON Korea. Engage customers, peers, and important decision-makers at this exclusive networking event.

Date: Jan 23(Wed), 2019
Time: 17:30-20:00
Room: #Grand Ballroom, 5F, InterContinental Seoul Parnas

Contact

Exposition team
Tel: +82-2-531-7800
Fax: +82-2-551-3406
Mail: semiconkorea@semi.org

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Keynote Speech

HK Kang

EVP and Head of research in Semiconductor R&D Center

Samsung Electronics

Keynotes Room 401, COEX Wednesday, January 23

10:10am to 12:10pm

Date: Jan 23(Wed), 2019
Time: 10:10-12:10
Room: #401, Conference Room (South), COEX
Registration: Free
Language: Korean and English (Simultaneous interpretation will be provided)

Agenda

10:10-10:40	The Role and Readiness of Semiconductor Technology for the 4^th Industrial Revolution (The slides will not be shared) HK Kang, EVP and Head of research in Semiconductor R&D Center Samsung Electronics Co.,Ltd

10:40-11:20	Phase-Change-Memory Devices for Non-von Neumann Computing (Click here to download) Evangelos Eleftheriou, Department Head, Cloud and Computing Infrastructure, IBM Research- Zurich

11:20-12:00	Nanotechnology Creating Magic (Click here to download) An Steegen, Executive Vice President Semiconductor Technology & Systems, imec

12:00-12:40	The Evolution from Chip Performance to System Performance (Click here to download) Ivo Bolsens, Sr. VP and CTO, Xilinx

*The agenda will be subject to change without notice.

* Presentation materials agreed by speaker will be distributed via e-mail after the events.

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Korea FPD Metrology TC Chapter Meeting

Standards SEMI Korea Office Friday, January 25

2:00pm to 4:00pm

Program: Korea FPD Metrology TC Chapter Meeting
Date: Jan 25(Fri), 2019
Time: 14:00-16:00
Room: SEMI Korea Office

Agenda

1.0 Welcome / Call to Order

1.1 Introductions
1.2 Meeting Reminders (Membership Requirement, Antitrust and Intellectual Property Reminders, Effective Meeting Guidelines)
1.3 Agenda Review

2.0 Review and Approval of Previous Meeting Minutes

3.0 Liaison Report

3.1 FPD Metrology Japan TC Chapter
3.2 FPD Metrology Taiwan TC Chapter

4.0 Staff Report

5.0 Ballot Review

None

6.0 Subcommittee & Task Force Reports

5.1 Perceptual Viewing Angle TF
5.2 Perceptual Image Quality TF
5.3 Transparent Display TF

7.0 Old Business

8.0 New Business

7.1 Discussion for roadmap

9.0 Action Item Review

10.0 Next Meeting and Adjournment

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Korea I&C TC Chapter Meeting

Standards Room 305, COEX Thursday, January 24

10:00am to 12:00pm

Program: Korea I&C TC Chapter Meeting
Date: Jan 24(Thu), 2019
Time: 10:00-12:00
Room: #305, Conference Room (South), COEX

Agenda

1.0 Welcome / Call to Order

1.1 Introductions
1.2 Meeting Reminders (Membership Requirement, Antitrust and Intellectual Property Reminders, Effective Meeting Guidelines)
1.3 Agenda Review

2.0 Review and Approval of Previous Meeting Minutes

3.0 Liaison Report

3.1 I&C Japan TC Chapter
3.2 I&C North America TC Chapter
3.3 I&C Taiwan TC Chapter

4.0 Staff Report

5.0 Ballot Review

5.1 4946D : Line Item Revisions to SEMI E87-1017, Specification for Carrier Management (Cms) and E87.1-1017 Specification for SECS-II Protocol for Carrier Management (CMS); Adding Carrier Ready to Unload Prediction Feature
5.2 5832A : New Standard, Specification for Equipment Generic Counter Model, (EGCM)
5.3 6301 : Line Item Revision to E142-0211, Specification for Substrate Mapping, Adding packaging raw materials traceability method

6.0 Subcommittee & Task Force Reports

6.1 GEM300 TF
6.2 DDA TF
6.3 ABFI TF

7.0 Old Business

8.0 New Business

9.0 Action Item Review

10.0 Next Meeting and Adjournment

Contact

Standards
Tel: +82-2-531-7808
Mail: eshim@semi.org

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Lithography Tutorial

Workforce Development Room 307, COEX Wednesday, January 23

9:00am to 12:00pm

Date: Jan 23(Wed), 2019
Time: 09:00-12:00
Room: #307, Conference Room (South), COEX
Theme:
Language:
Supported by

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Market Seminar

Market Room 318, COEX Wednesday, January 23

1:00pm to 5:00pm

New application is rising- AI, Automotive in semiconductor industry and it is time to look it up for understanding its impact in semiconductor market. Also, China market is still interesting theme for our industry due to its potential and investment scale. You can explore these issues as well as semiconductor equipment and materials outlook in one place!

Date: Jan 23(Wed), 2019
Time: 13:00-17:00
Room: #318, Conference Room (South), COEX
Language: English (Simultaneous interpretation will NOT be provided)
Who Should Attend:
- Senior Professionals in Marketing
- Sales
- Procurement
- Business Development
- Consulting and Product Planning
- Finance

Registration Fee

	SEMI Member	Non-Member	Student
Early Bird (by Jan 24)	150,000 won	180,000 won	80,000 won
Onsite	180,000 won	200,000 won	100,000 won

Agenda

10:00-10:30	The Next Memory Cycle: When, Why, and How it will Happen
	Jim Handy, Objective Analysis

10:30-11:00	The Rise of China IC Industry - As A Global Ecosystem Partner
	Lung Chu, SEMI China

11:00-11:20	Break

11:20-11:50	Market Dynamics Driving the Future of Automotive Semiconductors
	Jim Feldhan, Semico Research

11:50-12:20	Electronic Materials Trends in a Connected World
	Mark Thirsk, Linx Consulting

12:20-12:50	SEMI Market Outlook- Equipment & Materials for 2018
	Dan Tracy, SEMI

*The agenda will be subject to change without notice.

* Presentation materials agreed by speaker will be distributed via e-mail after the events.

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Meet the Experts!

Workforce Development Room 402, COEX Friday, January 25

1:00pm to 4:00pm

Date: Jan 25(Fri), 2019
Time: 13:00-16:00
Room: #402, Conference Room (South), COEX
Language:

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MEMS & Sensor Summit

SMART Room 300, COEX Friday, January 25

9:00am to 12:00pm

Date: Jan 25(Fri), 2019
Time: 09:00-12:00
Room: #300, Conference Room (South), COEX
Language: English and Korean (Simultaneous interpretation will NOT be provided)

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Metrology and Inspection Forum

Technology Room 402, COEX Thursday, January 24

10:00am to 5:00pm

As device technology shrinks to sub-10 nm, we expect a lot of challenges in process integration. Thus, many chip makers are considering EUV lithography to mitigate process risk and to reduce process integration time. However, EUV lithography also has many technical challenges. On the other hand, 3D memory process also brings another technical issue in many aspects. Therefore, we believe the role of Metrology & Inspection is getting more and more important to enable sub-10nm and 3D device.

This year, celebrating its 10^thanniversary, MI Forum will cover the theme as “MI: An Enabler of Future Devices” with technical experts from worldwide. We hope you can get better understanding on MI challenges and solutions for upcoming process technologies in the forum and build the network with industry leaders in MI Networking reception, which will be held after the forum as well.

Date: Jan 24(Thu), 2019
Time: 10:00-17:00
Room: #402, Conference Room (South), COEX
Theme:
Language:

Committee

Chuck Kim (AMETEK Korea)
Chang Woo Kim (KLA-Tencor Korea)
TK Kim (Semilab Korea)
Harris Kim (Rudolph Technologies Korea)
Munhong Ro (Dongbu HiTek)
Changman Moon (NOVA Measuring Instruments Korea)
Byong Chon Park (KRISS)
Dong Chun Lee (Nanometrics Korea)
Byoung-Ho Lee (SK hynix)
Suk Woo Martin Lee (Applied Materials Korea)
Sung Hun Lee (Thermo-Fisher MSD Korea)
Junwoo Lee (Auros Technology)
Jason Jeong (Nextin)
Jaesung Choi (ASML Korea)

Registration Fee

	SEMI Member	Non-Member	Student
Early Bird (by Jan 24)	200,000 won	240,000 won	120,000 won
Onsite	240,000 won	280,000 won	150,000 won

Agenda

10:00-10:10	Welcome

10:10-10:50	Keynote
	Metrology Inspection: Enabler for Future Devices Tuyen K. Tran, Intel

Session 1: EUV
10:50-11:20	Metrology Capabilities and Requirements for 7/5 nm Logic Manufacturing Benjamin Bunday, GLOBALFOUNDRIES

11:20-11:50	Holistic Patterning Solutions in Leading Edge Semiconductor Device Manufacturing Frank van de Mast, ASML

11:50-12:20	EUV Reticle Management: From Mask Shop to Fab Moshe Preil, KLA-Tencor

12:20-12:50	Metrology and Inspection Development in Imec Philippe Leray, Imec (invited)

12:50-14:30	Lunch (Lunchbox will be provided to attendees.)

Session 2: 3D
14:30-15:00	Managing Nanometers: In-line Control for 3D-Devices Kevin Heidrich, Nanometrics

15:00-15:30	MRAM HVM Metrology Challenge and Innovative MR Solution Lu Yu, KLA-Tencor

15:30-15:50	Break

15:50-16:20	Automated Nearline Workflows for 3D NAND Process Control Jack Hager, ThermoFisher Scientific

16:20-16:50	Optical CD: addressing current and future 3D challenges Igor Turovets, Nova Measuring Instruments

Session 3: Collaboration
16:50-17:20	Optical Metrology and Inspection Challenges for Memory Devices Seong-Min Ma, SK hynix (invited)

17:20-18:00	Panel Discussion

18:00-19:00	Networking Reception (Forum attendees are invited to networking reception.)

*The agenda will be subject to change without notice.

* Presentation materials agreed by speaker will be distributed via e-mail after the events.

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MI Reception

Networking Room 402 Lobby, COEX Thursday, January 24

5:00pm to 6:00pm

MI Reception is a special event for MI industry to build the global networking through supply chain and to get together for business opportunities. More than 200 people including MI Forum attendees, speakers and MI Committee members are expected to attend.

Date: Jan 24(Thu), 2019
Time: 17:30-18:00
Room: #402 Lobby, COEX

Contact

Program Team
Tel: +82-2-531-7806
Mail: koreaprograms@semi.org

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Opening Ceremony

Opening Ceremony Room 401, COEX Wednesday, January 23

10:00am to 10:10am

Opening Ceremony

Date: Jan 23(Wed), 2019
Time: 10:00-10:10
Room: #401, Conference Room (South), COEX

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Packaging Tutorial

Workforce Development Room 317 Thursday, January 24

9:00am to 12:00pm

Date: Jan 24(Thu), 2019
Time: 09:00-12:00
Room: #317, Conference Room (South), COEX
Language:

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Plasma & Etching Tutorial

Workforce Development Room 307, COEX Thursday, January 24

9:00am to 12:00pm

This short course tutorial is designed as basic course for new engineers who is working at etching technology related area. With the practical lecture from device makers, equipment suppliers and academia, you will learn the hottest issues and challenges in plasma & etching process and fundamental technologies as well.

Date: Jan 24(Thu), 2019
Time: 09:00-12:00
Room: #307, Conference Room (South), COEX
Language:

Agenda

09:00-09:45	Dry Etching Technology Evolution on Equipment and Process Jong Chul Park, Samsung Electronics

09:45-10:00	Break

10:00-10:45	Dry (Plasma) Etch Process in Semiconductor Device LeeJun Kim, Lam Research

10:45-11:00	Break

11:00-11:45	Research Trend of Atomic Layer Etching Prof. Geun Young Yeom, Sungkyunkwan University

*The agenda will be subject to change without notice.

*Proceeding will be provided at onsite.

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S1. Advanced Lithography

STS Room 307, COEX Wednesday, January 23

1:00pm to 5:00pm

Advanced Lithography session of the STS 2018 will offer the opportunities to review the latest trends in the mainstream lithography technologies under the theme of "EUV High Volume Manufacturing and Beyond".

Recently there are a lot of progresses achieved in EUV and as a result EUV is getting considered as a manufacturing means more seriously than before. For the sake of the solid migration to the manufacturing phase, the readiness of each component of EUV will be reviewed during this meeting including overview, exposure tools, optics, material, mask, and process by the prominent leading figures of the corresponding area. In addition, the next generation EUV technologies like high-NA EUV and EUV double pattering will be discussed to disclose the potential issues and to prepare collaboratively throughout the industry.

Date: Jan 23(Wed), 2019
Time: 13:00-17:00
Room: #307, Conference Room (South), COEX
Theme:
Language: English (Simultaneous interpretation will NOT be provided)
Supported by

Committee

Shangwon Kim (DB HiTek)
Seong-Sue Kim (Samsung Electronics)
Jaehyun Kim (Dongjin Semichem)
Hong Seok Kim (Toppan Photomasks Korea)
Chang-Nam Ahn (ASML Korea)
Hye-Keun Oh (Hanyang University)
Changmoon Lim (SK hynix)
Jaesung Choi (ASML Korea)

Registration Fee

	SEMI Member	Non-Member	Student
Early Bird (by Jan 24)	150,000 won	180,000 won	80,000 won
Onsite	180,000 won	200,000 won	100,000 won

Agenda

13:00-13:40	Current Challenges and Opportunities for EUV Lithography Timothy A. Brunner, GLOBALFOUNDRIES (invited)

13:40-14:20	EUV readiness, Insertion Opportunities and Challenges for Logic and Memory Philippe Leray, Imec

14:20-14:40	Metal Oxide Resists for EUVL: Improving Post-Etch Performance with Process Simplification Andrew Grenville, Inpria

14:40-15:00	EUV Material Solutions Ken Maruyama, JSR Corporation

15:00-15:20	Break

15:20-16:00	EUVL Optics: Status and Future Perspectives Winfried Kaiser, Carl Zeiss SMT (Invited)

16:00-16:20	Readiness of EUV Blanks Takahiro Onoue, HOYA Corporation

16:20-16:40	Maximizing EUV Photomask Lifetime with Backside Cleaning Bruce J. Fender, Applied Materials

16:40-17:00	Break

17:00-17:20	EUV lithography industrialization progress Rudy Peeters, ASML

17:20-17:40	EUV Resist Process Development to Achieve CD Uniformity with High Sensitivity Junghyung Lee, SK hynix

17:40-18:00	OPC Requirement and Development Status of EUV Lithography for Sub-7nm Technologies Jisuk Hong, Samsung Electronics

*The agenda will be subject to change without notice.

* Presentation materials agreed by speaker will be distributed via e-mail after the events.

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S2. Advanced Materials & Process Technology

STS Room 308, COEX Wednesday, January 23

1:00pm to 5:00pm

In this session, we will be able to share the most up-to-date research and development results in the field of Advanced Materials and Process Technology which are the key enablers of the future semiconductor devices. Many prominent authors from the academia and industries will cover various functional materials research area and semiconductor devices not only in the view point of the fundamental but also for the mass production. Especially, topics regarding material innovation for semiconductor application will be highlighted and technical challenges for mass production will be discussed. Excellent 8 presentations including 3 outstanding invited talks will be given and will cover the major technical issues and the leading edge solutions.

Date: Jan 23(Wed), 2019
Time: 13:00-17:00
Room: #308, Conference Room (South), COEX
Theme:
Language: English (Simultaneous interpretation will NOT be provided)
Supported by

Committee

Si Bum Kim (MagnaChip Semiconductor)
DeokSin Kil (SK hynix)
Hyoungyoon Kim (DB HiTek)
Jae Sung Roh (Jusung Engineering)
Kiseon Park (SK Materials)
Hyun Chul Sohn (Yonsei University)
Gill Lee (Applied Materials)
Marco Lee (Lam Research Korea)
Jong Min Lee (Eugene Technology)
In Gon Lim (Digital Imaging Technology)
HanJin Lim (Samsung Electronics)
Ji Hyun Choi (Tokyo Electron Korea)

Registration Fee

	SEMI Member	Non-Member	Student
Early Bird (by Jan 24)	150,000 won	180,000 won	80,000 won
Onsite	180,000 won	200,000 won	100,000 won

Agenda

13:00-13:40	Negative Capacitance Transistors Prof. Sayeef Salahuddin, University of California, Berkeley (invited)

13:40-14:00	Emerging of Memory and Logic Process Technology: Epitaxy Oh Hyun Kim, SK hynix

14:00-14:20	Materials and Process Innovation Enabling Logic Technology Roadmap Gaurav Thareja, Applied Materials

14:20-14:40	Core Technology in the Production of Heavily-doped Silicon Wafer for Power Device Do won Song, SK Siltron

14:40-15:00	Break

15:00-15:40	Area-selective Atomic Layer Deposition of SiO₂ and Ru for Self-aligned Fabrication Prof. Adrie Mackus, Eindhoven University of Technology (invited)

15:40-16:00	Emerging Memory Technologies: Materials, Devices and Architectures Alex Yoon, Lam Research

16:00-16:40	Ferroelectric HfO₂ - Material Fundamentals and Possible Applications Prof. Akira Toriumi, University of Tokyo (invited)

16:40-17:00	Evaluation of Deteriorations on Process-induced Damage of Cu/low-k Interconnect Structure Hideki Hashimoto, Toray Research Center

*The agenda will be subject to change without notice.

* Presentation materials agreed by speaker will be distributed via e-mail after the events.

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S3. Device Technology

STS Room 317, COEX Wednesday, January 23

1:00pm to 5:00pm

Semiconductor scaling is becoming increasingly challenging, requiring more than mere conventional dimension scaling. Two different approaches can be taken at this moment. One approach is to find new specific applications, such as automotive and IoT, based on the current technology. Another approach is to use innovative device structures to overcome the limitations of the current structure. This session will discuss such challenges and the exciting future that lies ahead with distinguished 6 speakers from all of the world.

Date: Jan 23(Wed), 2019
Time: 13:00-17:00
Room: #317, Conference Room (South), COEX
Theme:
Language: English (Simultaneous interpretation will NOT be provided)
Supported by

Committee

Oh-Kyong Kwon (Hanyang University)
Dong-Won Kim (Samsung Electronics)
Tae Kyun Kim (SK hynix)
Rock-Hyun Baek (POSTECH)
Changhwan Shin (University of Seoul)
Sang Gi Lee (DB HiTek)
Hi-Deok Lee (Chungnam National University)
Min Gyu Lim (MagnaChip Semiconductor)
Byung Jin Cho (KAIST)
Woo Young Choi (Sogang University)
Sung Woo Hwang (Samsung Advanced Institute of Technology)

Registration Fee

	SEMI Member	Non-Member	Student
Early Bird (by Jan 24)	150,000 won	180,000 won	80,000 won
Onsite	180,000 won	200,000 won	100,000 won

Agenda

13:00-13:40	Current Status and Trends in RF SOI Material and Device Prof. Jean-Pierre Raskin, Université Catholique de Louvain (invited)

13:40-14:10	Transistor Scaling Challenges and Opportunities to Pave for Single Digit Technology Node Namsung Kim, Applied Materials

14:10-14:40	Device Architectures beyond FinFET Keun Hwi Cho, Samsung Electronics

14:40-15:00	Break

15:00-15:40	CMOS Scaling based on FinFETs and Gate-All-Around Devices Hans Mertens, imec (invited)

15:40-16:20	Negative Capacitance Transistors: Physics, Materials and the State-of-Art Prof. Asif Khan, Georgia Institute of Technology (invited)

16:20-16:50	4Gbit Density STT-MRAM Using Perpendicular Magnetic Tunnel Junctions with Compact Bit Cell Structure Sooman Seo, SK hynix

*The agenda will be subject to change without notice.

* Presentation materials agreed by speaker will be distributed via e-mail after the events.

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S4. Plasma Science and Etching Technology

STS Room 307, COEX Thursday, January 24

1:00pm to 5:00pm

These days the semiconductor business is expanding more rapidly since Big Data and AI (Artificial Intelligence) technologies need plenty of chips as well as processor chips. Two technologies become the most promising ones for the future industry and they will change fundamentally the industrial structure and our normal lives all over the world. The skyrocketing needs for memories makes all chip makers to focus on scale down current DRAM, VNAND new memories. In addition, the high performance processors needs also more scale downed logic chips. As the scaling down is continuing, dry etching technology will confront the process limit eventually so it is the right time to discuss about the new etch technologies for overcoming the limit in this annual SEMICON symposium.

We prepared deep and wide touching on the critical and key etch technologies like new Pulsed Etch, ALE (Atomic Layer Etch), Ultra-high Energy Ion Etch, very-Low Temp. Etch and Etch Simulation technologies. These are essential technologies for solving the scaling down issue and, furthermore, for Big Data and AI era. We invited the academia and industry expertise who can share the vision and solutions for next generation etching technologies- please join us to gain keen insight of future.

Date: Jan 24(Thu), 2019
Time: 13:00-17:00
Room: #307, Conference Room (South), COEX
Theme:
Language: English (Simultaneous interpretation will NOT be provided.)
Supported by

Committee

Jaesoung Kim (DB HiTek)
Gyoungjin Min (Lam Research Korea)
Jongchul Park (Samsung Electronics)
Jong Won Shon (ASM Genitech)
Geun Young Yeom (Sungkyunkwan University)
Minsuk Lee (SK hynix)
IC Jang (Lam Research Korea)

Registration Fee

	SEMI Member	Non-Member	Student
Early Bird (by Jan 24)	150,000 won	180,000 won	80,000 won
Onsite	180,000 won	200,000 won	100,000 won

Agenda

13:00-13:40	MOL Etch Challenges at sub 10nm: Exploring ALE Process Regimes for High Selective SAC RIE Junsic Hong, GLOBALFOUNDRIES (invited)

13:40-14:10	Patterning Challenges and Perspective Solutions for 5nm and Beyond Ying Zhang, Applied Materials

14:10-14:50	Using Plasmas in the Semiconductor Industry Prof. Rod Boswell, Australian National University (invited)

14:50-15:20	New Approach Using Plasma Information Variables to Develop Virtual Metrology of Cr-Etch Process Prof. Gon-Ho Kim, Seoul National University (invited)

15:20-15:40	Break

15:40-16:00	The Historical Trend of HARC Etching Technology and New Challenges Yoonjae Tyler Kim, Samsung Electronics

16:00-16:40	Addressing Challenges in Selectivity and High Aspect Ratio Plasma Etching Through Modeling Prof. Mark J. Kushner, University of Michigan (invited)

16:40-17:10	Current Status of Etching Process Diagnostics and Simulation based on Scientific Data Jung-Sik Yoon, National Fusion Research Institute (invited)

17:10-17:30	Atomic Layer Etch - Plasma Etch with Precision Yoojin Kim, Lam Research

*The agenda will be subject to change without notice.

* Presentation materials agreed by speaker will be distributed via e-mail after the events.

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S5. Contamination-free Manufacturing and CMP Technology

STS Room 308, COEX Thursday, January 24

1:00pm to 5:00pm

Continuous shrinkage of device dimension to nm level requires new materials and novel device structure which demand a new paradigm in contamination control and planarization to improve the production yield and device reliability. CFM technology has become more critical in device manufacturing below 20 nm devices. Film loss-free and damage free cleaning technology face severe challenges for next-generation device fabrication. Also, CMP has grown to be one of the essential technologies for advanced node device fabrications such as FinFET, III/V materials and V-NAND. 7-nm logic technology is already under developing now, and CMP will play the leading role on patterning for sub-7 nm FEOL and MOL process steps. To overcome the new CMP challenges, the consumables should play a more critical role. The purpose of this session is to increase the level of understanding on current and future CFM/CMP technology.

Date: Jan 24(Thu), 2019
Time: 13:00-17:00
Room: #308, Conference Room (South), COEX
Theme:
Language:
Supported by

Committee

Kyunghyun Kim (Samsung Electronics)
Sang Yong Kim (Korea Polytechnics)
Ho Youn Kim (DB HiTek)
Jin-Goo Park (Hanyang University)
Haedo Jeong (Pusan National University)
Hong, Chang-Ki (Versum Materials)
Kyungho Hwang (SK hynix)

Registration Fee

	SEMI Member	Non-Member	Student
Early Bird (by Jan 24)	150,000 won	180,000 won	80,000 won
Onsite	180,000 won	200,000 won	100,000 won

Co-organized by	Korea CMP UGM
	Korea Surface Cleaning UGM (KSCUGM)

Agenda

Session 1: CFM Technology

13:00-13:40	Challenges for Chemical Processing of High Aspect Ratio Nanostructures Guy Vereecke, imec (invited)

13:40-14:00	The Study of Post Cleaning Treatment after Chemical-mechanical Polishing in DRAM Device Sangsoo Kim, SK hynix

14:00-14:20	Process Modification for Effective Removal of Byproduct at Drycleaning Jaejin Shin, Samsung Electronics

14:20-14:40	Advanced Un-pattern Wafer Inspection for Process Control Keebum Jung, KLA-Tencor

14:40-15:00	Break

Session 2: CMP Technology

15:00-15:40	Recent Trend of CMP Equipment Platform and its Requirement of Processes and Consumables: BEOL CMP Sunghoon Lee, GLOBALFOUNDRIES (invited)

15:40-16:00	Surface Roughness Control Technology of W CMP Process Heesook Cheon, Samsung Electronics

16:00-16:20	Chemical Mechanical Polishing (CMP) Process Stabilization through Enhanced Inline Monitoring Tech in Three Dimension-Stacking NAND Flash Memory Deok Yeon Lee, SK hynix

16:20-16:40	Future Trends and Inflections in CMP System Control & Performance Sidney Huey, Applied Materials

16:40-17:00	Advanced Data Analysis Strategies for Understanding Particle Contamination in Chemical Distribution Systems Dan Rodier, Particle Measuring Systems

*The agenda will be subject to change without notice.

* Presentation materials agreed by speaker will be distributed via e-mail after the events.

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S6. Electropackage System and Interconnect Product

STS Room 317, COEX Thursday, January 24

1:00pm to 5:00pm

As packaging, wafer level and heterogeneous system assembly in general, electronic systems for future mobility, 5G, AI and Automotive are targeting to find solutions for those key critical aspects of packaging: Performance, Flexibility and Cost competitiveness. Those solutions will make huge connection among system and system such as sensor and logic, logic and memory, antenna and logic. So we are expecting to make a new vision era how packaging as a SIP, FOWLP, 3D IC, and 2.5D IC will open to new market as a heart of 4th industry generation. To address those, chip-packaging-system interaction needs to be better understood. The experts of device design, FABs engineering, packaging, and system need to move closer together. Materials and Equipments need to be developed and tested for electronic systems. Those are the challenging but this session is helping to share the recent advanced packaging information.

Date: Jan 24(Thu),2019
Time: 13:00-17:00
Room: #317, Conference Room (South), COEX
Theme:
Language:
Supported by

Committee

Gu Sung Kim (Kangnam University)
Young Bae Park (Andong National University)
Min Suk Suh (SK hynix)
Hogeon Song (Samsung Electronics)
WS Shin (ASE Korea)
Seh Kwang Lee (Ehwa Diamond)
Hanchoon Lee (DB HiTek)
Ji Young Chung (Amkor Technology Korea)
Soon Jin Cho (Samsung Electro-Mechanics)
Taeje Cho (Samsung Electro-Mechanics)
CS Han (ASE Korea)

Registration Fee

	SEMI Member	Non-Member	Student
Early Bird (by Jan 24)	150,000 won	180,000 won	80,000 won
Onsite	180,000 won	200,000 won	100,000 won

Agenda

13:00-13:30	Material Trends in Advanced Packaging Santosh Kumar, Yole Développement

13:30-14:00	Challenges and Opportunities in Advanced Package of Automotive Electronics Seung wook Yoon, StatsChipPAC

14:00-14:20	Bump Electromigration Reliability of Fine Pitch Interconnects Seunghyun Chae, SK hynix

14:20-14:40	Evolving in Fan-Out Technology for Next Generation Applications YoungRae Kim, Amkor Technology Korea

14:40-15:00	Break

15:00-15:30	NVIDIA Strategy for AI & AD Revolution Junghoon Cha, NVIDIA (invited)

15:30-15:55	Strategies for Mechanically Reliable Thin-Film Flexible Electronics Prof. Taek-Soo Kim, KAIST (invited)

15:55-16:15	Electrical Performance Analysis of RDL Package Se-Ho You, Samsung Electronics

16:15-16:35	Ion Beam Source for RDL Pre-Clean in Fan-Out Wafer and Fan-Out Panel Level Packaging Paul F. Werbaneth, Intevac

16:35-16:55	Break

16:55-17:25	Packaging Integration of 60GHz Antenna Array Using Silicon to Package Co-design Flow Christian Goetze, GLOBALFOUNDRIES (invited)

17:25-17:45	2.5DIC Technology and Solutions Oscar Shih, ASE

17:45-18:05	Advanced Technology Developments in Samsung’s Panel Level Package Jeongsoo Byun, Samsung Electro-mechanics

18:05-18:25	Panel Level Packaging New Era Advanced Packaging Solution Tae-Hoon Kim, nepes

*The agenda will be subject to change without notice.

* Presentation materials agreed by speaker will be distributed via e-mail after the events.

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SMART Manufacturing Forum

SMART Room 300, COEX Thursday, January 24

1:00pm to 5:00pm

Technology is evolving at lightning speed – faster than ever before. The increasing adoption of IoT technologies, robotics, automation, software and data analytics means that virtually all industries and sectors are set to experience significant change. Even semiconductor industry which is well-known as highly automated manufacturing also continues to pursue smarter solutions in order to overcome various new challenges in an increasingly complexed fab operation environment.

In this forum, presenters from all over the world will share their insights on the latest trends and emerging technologies in Smart Manufacturing areas such as IoT, Cloud Computing, Big Data, Machine Learning, and Artificial Intelligence focusing on implications in semiconductor industry. They will also illustrate the benefits of realizing “Smart Manufacturing” through the adoption of new methods, new systems, and new solutions.

Date: Jan 24(Thu), 2019
Time: 13:00-17:00
Room: #300, Conference Room (South), COEX
Language: English and Korean (Simultaneous interpretation will NOT be provided)

Registration Fee

	SEMI Member	Non-Member	Student
Early Bird (by Jan 24)	150,000 won	180,000 won	80,000 won
Onsite	180,000 won	200,000 won	100,000 won

Agenda

13:00-13:30	Applying Recent IT Technology to Smart Manufacturing Innovation Kyoung Shik Jun, BISTel

13:30-14:00	Beyond Full Automation Jan Rothe, GLOBALFOUNDRIES

14:00-14:30	IoT for SECS and Non-SECS Equipment in Semiconductor Backend Manufacturing Teck Khiong Woi, Infineon Technologies AP Pte Ltd

14:30-15:00	Break

15:00-15:30	Lam Equipment Intelligence Enabling Productivity and Performance Jason Shields, Lam Research

15:30-16:00	Powering the Digital Economy James Chae, Schneider Electric

16:00-16:20	Smart Manufacturing & SEMI Tom Salmon, SEMI HQ

16:20-16:30	Q&A

*The agenda will be subject to change without notice.

* Presentation materials agreed by speaker will be distributed via e-mail after the events.

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Test Forum

Technology Room 318, COEX Thursday, January 24

1:00pm to 5:00pm

The 5G and Big Data, key issues in next connected world are increasing demand for putting more pressure on test costs due to higher coverage requirements. Test must become smarter to address the increased quality demands, while at the same time remaining economical. To address these challenges, test industry is struggling with increasing instrumentation integration, smarter strategies, self-test, adaptive test, system-level test, as well as more sophisticated test hardware. In this Test Forum, you can get the clues to overcome these challenges from industry expertise.

Date: Jan 24(Thu), 2019
Time: 13:00-17:00
Room: #318, Conference Room (South), COEX
Language: English and Korean (Simultaneous interpretation will NOT be provided)

Committee

Young-Kwan Ko (UniTest)
James Jin-Soo Ko (Teradyne)
Kwonsung Ban (Samsung Electronics)
JeongBeom Bae (FormFactor Korea)
Sokyoung Song (SK hynix)
Kyu-hyuk Yeon (ASE Korea)
MinHo Chang (Amkor Technology Korea)
YH Jeon (TSE)
Jeongho Cho (Advantest Korea)

Registration Fee

	SEMI Member	Non-Member	Student
Early Bird (by Jan 24)	150,000 won	180,000 won	80,000 won
Onsite	180,000 won	200,000 won	100,000 won

Agenda

13:00-13:40	Automotive Test & Reliability Yervant Zorian, Synopsys (invited)

13:40-14:10	5-Gen, RF Testing Solutions Ok-Su Kim, Advantest

14:10-14:40	Big Data and Semiconductor Test Gregory S. Smith, Teradyne (invited)

14:40-15:00	Break

15:00-15:40	Towards 5G HetNet and IoT: Stakes, Challenges and Key Enabling Technologies Cedric Dehos, CEA-LETI (invited)

15:40-16:10	Key Trends Driving the Need for More System-Level Test Anil Bhalla, Astronics Test Systems

16:10-16:40	Why Have Test Costs Stopped Going Down? Ken Lanier, Teradyne

16:40-17:10	ISO 26262 and Soft Error Sung S. Chung, QRT

*The agenda will be subject to change without notice.

* Presentation materials agreed by speaker will be distributed via e-mail after the events.

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VIP Luncheon -Invitation Only

Networking Room 403, COEX Wednesday, January 23

12:30pm to 1:30pm

Date: Jan 23(Wed), 2019
Time: 12:30-13:30
Room: #403, Conference Room (South), COEX

Contact

Exposition team
Tel: +82-2-531-7800
Fax: +82-2-551-3406
Mail: semiconkorea@semi.org

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