4Gbit Density STT-MRAM Using Perpendicular Magnetic Tunnel Junctions with Compact Bit Cell Structure
Spin transfer torque Magnetic Random Access Memory (STT-MRAM) has attracted increasing attention as a potential replacement for Dynamic Random Access Memory (DRAM) due to infinite endurance, fast operation, and extended scalability beyond 30nm feature dimension [1-4]. Furthermore, STT-MRAM enable to overcome the excessive power consumption of DRAM by taking advantage of the nonvolatile data stored in magnetic tunnel junction (MTJ).
In particular for high density STT-MRAM, the mature integration technology and high performance MTJ are essential based upon an extremely tight pitch. From the viewpoint of memory operation, the distribution of parasitic resistance should be significantly improved. In this work, we demonstrate 4Gbit density STT-MRAM with optimization of integration process and MTJ fabrication .
The unit bit cell consists of a NMOS transistor, a pair of bit line (B/L), a circle-shape MTJ, source line (S/L), and all perpendicular MTJ utilizing CoFeB/MgO/CoFeB based MTJ and the magnetic multilayer. The bottom-storage layer is adapted to prevent the degeneration of current drivability for parallel-to-antiparallel switching. Within 90nm-pitch, the cell projection area using 3-dimensional transistor is estimated as 9F2.
The impact of parasitic resistance on memory window is examined by using the bit cell array excluding MTJ. We found that the contact process is critical to enhance read operation window. Write error rate (WER) evaluation was performed for several kbits with 106 cycles. The optimized fabrication process and MTJ stacks allow to sufficiently suppress the average WER for a reliable write operation. 4Gbit full-functional operation was performed after replacing failure bits with redundancy cells. Our achievement paves the way toward stand-alone memory application of STT-MRAM.
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