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논문 모집

 

제 30회 국제 반도체장비재료 전시회인 SEMICON Korea 2017와 병행하여 개최되는 SEMI 기술심포지움(이하 STS)에서 발표될 논문을 모집합니다. 본 심포지움은 국내외 소자업체, 반도체 장비 및 재료 업체의 기술전무가, 학계 전문가들 그리고 학생들이 한자리에 모여 반도체 생산 공정의 최신 기술을 소개하고 앞으로의 기술 동향 및 정보 교환을 그 취지로 하고 있습니다.

소자업체, 장비 및 재료 업체에 종사하는 기술 실무진과 관련 분야에 있는 학계 분이라면 누구든 참여하실 수 있습니다. 논문 초록의 접수 후 10월 말까지 각 분과의 위원들의 심사를 거쳐 발표여부가 결정이 되며 그 이후에는 일정에 맞추어 논문과 발표자료를 제출하시면 됩니다.

매년 STS에서는 한국 및 전세계 향후 반도체 기술의 방향을 제시하고, 반도체 산업 현황 및 발전 가능성에 관하여 심도 깊은 논의가 이루어져 왔습니다. 논문발표 기회와 더불어 세계 반도체 전문가와 교류하는 SEMI 기술심포지움에 반도체 전문가 분들의 많은 참여를 부탁드립니다.

모집하고있는 논문의 분야는 하기와 같습니다. 

S1. Advanced Lithography

  • Resist Processes and Materials
  • Photomask Processes and Materials
  • Design Process Technology Co-Optimization for Manufacturability
  • Various Multiple Patterning Techniques
  • Advanced Metrology Technology for Wafer and Mask
  • Extreme Ultraviolet Lithography
  • Directed Self Assembly
  • Alternative Lithography (Nano-Imprint and others)
  • Application of Lithography to Nanotechnology

 

S2. Advanced Process Technology: Dielectrics, Metals, and Other Materials 

    • Advanced Gapfill Technology
    • Interconnection (Interconnect/Barrier Metal, Gate Electrode, Salicidation, Optical Interconnection)
    • Dielectric (high k, low k, Gate Dielectric, Ferroelectric, Passivation)
    • Doping & Heat Treatment Process (I2p, Plasma Doping, GILD, SADS, RTP, Furnace, Damage Control)
    • Epitaxial Growth (Blanket, Selective, Device Integration)
    • SOI Materials & Processes (Wafer Manufacturing, Device Manufacturing)
    • Materials and Process for Non Volatile Memory Devices (PCRAM, STT-RAM, ReRAM, 3D-NAND, 3D X-point)
    • Nano Process Technology (Quantum Dot/Nanowire/Layer Formation)
    • 2D Materials (Graphene, Sulfide, and etc.)
    • Materials and Process for Beyond Moore

     

    S3. Device Technology

      • A.I.-friendly Device Technology
      • SoC Technology
      • Advanced CMOS Technology
      • Advanced Memory Technology
      • SOI Devices
      • RF Devices
      • Nano-scale Devices
      • Thin Film Devices
      • Interconnection Technology
      • Advanced Junction/Doping Technology
      • Process/Device/Interconnection Modeling
      • Device/Interconnection Reliability
      • Device Technology for Mobile/ Automotive Application

         

        S4. Plasma Science and Etching Technology

          • 3D Etch Technologies for VNAND, 3D X-point, FinFET, Nano Wire, TSV and etc.
          • New & Novel Material Etch for MRAM, PRAM, ReRAM, and etc.
          • Patterning Etch Technologies related to DPT, QPT, DSA, EUV and etc.
          • Selective Etch Technique
          • Atomic Layer Etching (ALE) and Low Damage Etching (LDE)
          • Etch Technologies related to FEOL (FiNFET Gate etc.) and BEOL (SAC, Low-k etc.)
          • HARC & HART Etch Technology
          • New Plasma Tools and New Unit Technologies (Pulsing, Fast MFC, Low-temp chiller, TMP, etc.)
          • Tool to Tool Matching (TTTM) Technologies
          • Plasma & Process Diagnostics, Sensors, and Control
          • Simulation and Modeling for Plasma Source and Process 
          • Innovative Approaches to Atomic Layer Material Removal

           

          S5. Contamination-Free Manufacturing and CMP Technology

            • Advanced Wet/Dry Surface Preparation in FEOL/BEOL
            • Micro-, Nano-contamination Control
            • Damage/Loss Free Nano Particle Removal
            • Yield Enhancement Technology
            • Environmentally Benign Manufacturing/PFC Emission Reduction
            • Advanced Wet/ Dry Cleaning for 3D Structure and New Materials
            • Advances in CMP, Related Processes and Equipments
            • CMP Consumables and Metrology
            • Scratch Reduction/Mechanism
            • CMP Modeling and Simulation 
            • Post CMP Cleaning

               

              S6. Electropackage System and Interconnect Product

              • Advanced Wafer Level Fan-out Technology 
              • Ultra Thin PoP Technology Using Advanced Wafer Level Fan-out
              • Wafer Warpage Control Technology
              • Memory Stack Technology, Package-on-FoWLP (WLFO) Technology
              • Multi-chip-integration in FoWLP (WLFO)
              • Board Level Reliability with FoWLP (WLFO)
              • Small 3D Form Factor SiP
              • RF MEMS WLP Solution
              • PLP (Panel Level Package) Technology
              • Wafer Molding Technology
              • Wafer Supporting Technology

               

              Submit an Abstract 

              논문모집은 2016년 9월 30일에 마감되었습니다. 

               

              Guidelines

              • 500자 내외의 초록과 100자 내외의 바이오그래피 제출
              • 발표제목/초록이 정확하여야 하며 논문 내용은 상업적인 회사/기술 홍보를 배제한 기술적이고 전문적인 부분을 중심으로 구성되어 있어야 발표 가능

               

              Important Date 

              추후 안내 드리겠습니다. 

               


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