CMOS Scaling based on FinFETs and Gate-All-Around Devices
Advanced CMOS scaling requires power, performance and area improvements for every new technology node. A key enabler for area scaling in the front-end of line is the reduction of the contacted gate pitch (CGP), which is composed of (1) gate length, (2) spacer width, and (3) contact width. Downscaling of these three elements causes several power-performance challenges that need to be addressed by material and device architecture innovations. In this talk, we will describe several of these innovations for both FinFETs and gate-all-around devices. The latter are promising candidates to replace FinFETs in future CMOS technology nodes. In addition, the scaling benefits of some of process improvements will be reviewed from a design technology co-optimization (DTCO) perspective.