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EUV readiness, Insertion Opportunities and Challenges for Logic and Memory

EUV readiness, Insertion Opportunities and Challenges for Logic and Memory

EUV readiness, Insertion Opportunities and Challenges for Logic and Memory

 

The development of EUV lithography was a long, challenging and bumpy road, but recent results obtained in term of source power and stability has open a path to industrialization. This path is needed as the pitch scaling is under strong pressure and EUV would be a good solution for patterning and cost purpose. But still some challenges are in front of us: Resist and Infrastructure.
In this paper, after an overview of the landscape of the patterning development sustaining the Moore’s law, we will show the most recent results obtained for EUV source and reliability improvement and the mask defectivity improvements achieved. Then we will describe the issue of stochastic effects that are impacting severely the EUV lithography. Finally, after the description of the hypothesis of physical/chemical mechanisms that seem to drive this problem, we will list all the initiative currently ongoing in imec to enable EUV lithography by reducing the number of stochastic counts.

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