Materials and Process Innovation Enabling Logic Technology Roadmap
PPARC – Power, Performance, Area, Reliability and Cost are the defining metrics for logic technology roadmap. Within the scope of these metrics, complex logic circuits are designed with aggressive design rules. These dimensionally scaled circuits are realized with advanced 3D transistor and interconnect fabrication processes which have multiple issues such as high capacitance/resistance, pitch walking and edge placement errors. These issues impact product performance, yield, reliability, cost and time to market. This talk will present logic technology inflections and novel process solutions using multi-color material library design, selective etch/dep processes, high throughput equipment and advanced metrology to achieve the desired PPARC.