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Metrology Inspection: Enabler for Future Devices

Metrology Inspection: Enabler for Future Devices

Metrology Inspection: Enabler for Future Devices

 

Many advancements in the art of defect detection on either bare silicon wafers or patterned wafers were strongly driven by the need to be able to reliability and systematically detect defects which negatively impact yield. As Moore’s Law is relentlessly pursued, the need to be able to detect ever smaller defects also grows exponentially strong, pushing the envelope of state-of-the-art solutions in many areas such as lasers and optics, in detector development, in defect detection algorithmic development and in numerous other areas that are required to maintain and improve a defect inspection system. The net challenge in yield improvement is always being able to identify accurately yield limiting sources in a timely manner, and at a cost that is affordable. For advanced process Fabs, this becomes an even larger concern as there is a delicate line to walk between managing the cost of defect inspection system used to improve yield internally and maintain enough of an effective supplier pool from which equipment development efforts are primarily undertaken. Strictly pushing for the lowest cost possible with an equipment supplier maybe successful for a generation or two of defect inspection technology, but may not in the long term produce the proper kind of environment in which equipment suppliers would feel compelled to further developing new technology to support their leading-edge customers, for whom there are fewer to begin with.
Entering the critical phase of Moore’s law in which process development routinely encounters fundamental barriers of physics, while defect inspection technologies becomes exponentially more expensive and time consuming to develop, and still delivering more limited returns on investment, our industry need to focus our collective effort to overcome current engineering challenges of designing and employing cost effective inspection scheme which address both random and systematic defects that the industry needs as it strives to go below sub-5nm process development.
This presentation reviews Unpatterned and Patterned defect inspections for semiconductor metrology. It covers current darkfield, bright field, and electron-based state-of-the-art inspection technologies. The goal is to articulate key aspects of random vs. systematic defect inspection and their inherent technology limitations on different substrate materials.

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