Optical CD: Addressing Current and Future 3D Challenges
During the last few years many questions have been asked about the limits of conventional scaling (Moore’s Law) and about the industry’s ability to manufacture and measure smaller and smaller devices. Currently, for logic we can see that Moore’s Law is struggling to scale down to the 5 and 3nm nodes; however, for memory the battle has already been lost: by now we have seen a few generations of vertical NAND inside our smart phones—meaning that advances in planar NAND memory are over.
Going vertical creates new integration challenges and requires more advanced metrology to allow high volume production. In our presentation we will discuss how scatterometry is addressing current metrology challenges of 3D VNAND in R&D and production, and also how scatterometry helps the development of revolutionary 3D logic devices based on nanowires—both horizontal and vertical.