S6. Electropackage System and Interconnect Product

Room #317, COEX Thursday, February 01
1:00pm to 5:00pm

Language: English (Simultaneous interpretation will NOT be provided)


  SEMI 회원사 비회원사 학생
사전등록(2/1까지) 150,000 원 180,000 원 80,000 원
현장등록 180,000 원 200,000 원 100,000 원


Continuous shrinkage of device dimension to nm level requires new materials and device structure which demand a new paradigm in contamination control and planarization to improve the production yield and device reliability. CFM technology has become more important in device manufacturing below 20 nm devices. Film loss free and damage free cleaning technology face to serious challenges for next generation device cleaning. Also CMP has grown to be one of the indispensable technologies for advanced node device fabrications such as FinFET, III/V materials and V-NAND. 7-nm logic technology is already under developing now; and CMP will play the main roll on patterning for sub-7 nm technology. In order to achieve the advanced process successfully, it is essential to make the combination among consumable parts in CMP. The purpose of this session is to increase the level of understanding on current and future CFM/CMP technology. Therefore, we are trying to share our intensive and profound perspectives through some remarkable speeches here.


  • Gu Sung Kim (Kangnam University)
  • Young Bae Park (Andong National University)
  • Minsuk Suh (SK hynix)
  • WS Shin (ASE Korea)
  • Seh Kwang Lee (Ehwa Diamond)
  • Hanchoon Lee (Dongbu HiTek)
  • Ji Young Chung (Amkor Technology)
  • Soon Jin Cho (Samsung Electro-Mechanics)
  • Taeje Cho (Samsung Electronics)
  • CS Han (ASE Korea)


13:00-13:30 Where Is the Destination of the Packaging Technology?
  Choon Heung Lee, Lam Research (invited)
13:30-14:00 Market and Technology Trends of Wafer Level Packages
  Santosh Kumar, Yole Developpement
14:00-14:40 High Density Package Integration by WLFO based WLSiP and WLPoP
  Steffen Kroehnert, NANIUM (invited)
14:40-15:00 Break 
15:00-15:20 Study on the Characteristics of Low Temperature Chemical Vapor Deposited Silicon Nitride and Silicon Oxide Film in through Silicon via Bumping Process
  Ju-heon Yang, SK hynix
15:20-15:40 Advanced eWLB/FO-WLP (embedded Wafer Level Ball Grid Array/FanOut-Wafer Level Package) for High Frequency Applications
  Seung Wook Yoon, STATS ChipPAC
15:40-16:00 A New Wave Fan-Out Package for Heterogeneous Integration
  Walter Jau, ASE
16:00-16:20 Break
16:20-17:00 Adaptive Patterning for Multi-chip WLFO
  Christopher Scanlan, Deca Technologies (invited)
17:00-17:20 Low Temperature Dielectric Material Challenges for 3D Wafer-Level Packaging Applications
  Jinho An, Samsung Electronics
17:20-17:40 Silicon-Less Integrated Module (SLIM™) for Mobile Applications
  Wonchul Do, Amkor Technology Korea


*상기 일정은 사전 안내 없이 변경될 수 있습니다.

* 발표 자료는 당일 컨퍼런스 종료 후 사이트를 통해 배포됩니다 (연사가 동의하지 않는 경우는 배포되지 않음).

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