S6. Electropackage System and Interconnect Product


Recent Advances in Wafer Level Packaging 

  • 날짜: 2017년 2월 9일 목요일
  • 시간: 오후 1시 - 오후 5시 40분
  • 장소: 코엑스 3층 컨퍼런스룸(남) 317호
  • 언어: 영어 (동시통역은 제공되지 않음)


  SEMI 회원사 비회원사 학생
사전등록(2/1까지) 150,000 원 180,000 원 80,000 원
현장등록 180,000 원 200,000 원 100,000 원


As customers demand for new electronic devices and performance enhancement, high-tech technology is required for package process which was treated as simple manufacturing in the past. In the meantime, advanced wafer-level packaging is attracting attention as a future technology for Internet (IoT) and mobile devices. This is due to its high cost competitiveness compared to existing packaging processes and the ability to package System in packages (SIPs), in which multiple chips and passive components are placed in one package in order to configure the system. In this session, you will find the deep knowledge and opportunities for the recent advances in wafer-level packaging in the market




Gu Sung Kim (Kangnam University)
Young Bae Park (Andong National University)
Minsuk Suh (SK hynix)
WS Shin (ASE Korea)
Seh Kwang Lee (Ehwa Diamond)
Hanchoon Lee (Dongbu HiTek)
Ji Young Chung (Amkor Technology)
Soon Jin Cho (Samsung Electro-Mechanics)
Taeje Cho (Samsung Electronics)
CS Han (ASE Korea)



13:00-13:30 Where Is the Destination of the Packaging Technology?
  Choon Heung Lee, Lam Research (invited)
13:30-14:00 Market and Technology Trends of Wafer Level Packages
  Santosh Kumar, Yole Developpement
14:00-14:40 High Density Package Integration by WLFO based WLSiP and WLPoP
  Steffen Kroehnert, NANIUM (invited)
14:40-15:00 Break 
15:00-15:20 Study on the Characteristics of Low Temperature Chemical Vapor Deposited Silicon Nitride and Silicon Oxide Film in through Silicon via Bumping Process
  Ju-heon Yang, SK hynix
15:20-15:40 Advanced eWLB/FO-WLP (embedded Wafer Level Ball Grid Array/FanOut-Wafer Level Package) for High Frequency Applications
  Seung Wook Yoon, STATS ChipPAC
15:40-16:00 A New Wave Fan-Out Package for Heterogeneous Integration
  Walter Jau, ASE
16:00-16:20 Break
16:20-17:00 Adaptive Patterning for Multi-chip WLFO
  Christopher Scanlan, Deca Technologies (invited)
17:00-17:20 Low Temperature Dielectric Material Challenges for 3D Wafer-Level Packaging Applications
  Jinho An, Samsung Electronics
17:20-17:40 Silicon-Less Integrated Module (SLIM™) for Mobile Applications
  Wonchul Do, Amkor Technology Korea


*상기 일정은 사전 안내 없이 변경될 수 있습니다.

*발표 자료는 당일 컨퍼런스 종료 후 사이트를 통해 배포됩니다 (연사가 동의하지 않는 경우는 배포되지 않음). 

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