Since 2016, Gaurav Thareja is a Senior Manager of the Patterning and Packaging CTO group at Applied Materials.
From 2011 - 2016, as an Intel 10nm PTD integration engineer, he led various cross functional teams comprising of process, TCAD, reliability, device, failure analysis and developed state of the art logic transistor processes.
He got a PhD in Electrical Engineering from Stanford University in 2011. He has co-authored more than 20 papers in referred conferences / journals and 10 US patents published/pending.
본 연사의 발표는 S2. Advanced Materials & Process Technology(STS) 에서 볼 수 있습니다.