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Transistor Scaling Challenges and Opportunities to Pave for Single Digit Technology Node

Transistor Scaling Challenges and Opportunities to Pave for Single Digit Technology Node

Transistor Scaling Challenges and Opportunities to Pave for Single Digit Technology Node

 

FinFET has been an excellent device architecture used to enable the continuous scaling by offering power and performance improvement thanks to superb electrostatic control to meet the PPAC (power, performance, area and cost) requirement of each technology node. However, the biggest roadblocks & ongoing challenges of scaled FinFET are sub-Fin leakage current control, parasitic resistance and capacitance management; all of which are under tremendous engineering efforts to pave for continuous scaling opportunity to next node. This talk will describe CMOS logic transistor scaling challenges from Scaled FinFET to potential GAA (Gate-All-Around) device architecture as well as introduce some of the key enablers as performance boosters driven by material and process module innovations.

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