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Plasma Etching Technology Challenges for Next Generation Devices

3:50 pm - 4:10 pm

For the improvement of device performance and power consumption, the dimension of semiconductor devices has been shrinking with Moore’s law (the number of chips will be double every 18 months). However, with reaching physical limits of scaling trend including logic and memory devices, the accuracy of etching technology became more critical. For overcoming the issues of High Aspect Ratio Structures and Residue issue of byproducts, more sophisticated tuning knobs such as radical flux, ion flux, ion energy, sync (async) pulsing, multilevel pulsing and ion energy distribution control will be necessary. Device will degrade more often than before due to wrong plasma conditions. In addition, the defect performance such as wiggling, leaning and roughening will depend on the etching profile with atomic level accuracy. Alternative etching solutions including new physical improvement from etch equipment will be essential to achieve the required criteria for extending device scaling.



Huichan Seo

Technical Leader, SK hynix

Huichan Seo, Ph.D. has been Technical Leader at SK Hynix for 2 years with responsibility for DRAM Front-End Patterning, which includes ISO STI, Buried Gate and High-k metal gate etching. Prior to joining SK Hynix, Seo was Senior Process Engineer at Intel. During his 10 years at Intel, Seo had responsibility for Tri-Gate Pattering, Fin Patterning and other Pathfinding Projects. He got 2 times IAA (Intel Achievement Award) for his great contribution on 3D transistor patterning and Device performance enhancement. Seo received a Ph.D. degree in Material Science and Engineering from University of Illinois at Urbana-Champaign, Champaign, IL, USA and Master/Bachelor degree in Material Science and Engineering from Seoul National University, Korea.