Skip to main content

Enabling Vertically Integrated Memories with Co-optimized Deposition and Etch Solutions

2:00 pm - 2:20 pm

The semiconductor industry needs new levers to scale across all device types. Vertical scaling is one of the approaches. 3D NAND Flash is the first embodiment of vertically integrated memories. Emerging storage class memories are following suit. To vertically scale memory devices, the biggest challenges are to deposit new materials with the required uniformity, to deposit thin conformal films with atomic level precision and to etch new structures and high aspect ratio holes and trenches with high CD uniformity. In this presentation, we will cover deposition and etch challenges and co-optimized solutions of vertically integrated memories.


T Lill

Thorsten Lill

Vice President, Integrated Technologies and Systems, Lam Research

Thorsten Lill is VP of Integrated Technologies and Systems at Lam Research. He holds a Ph.D. in Physics from the Albert Ludwigs University of Freiburg, Germany.

In Freiburg, he studied collisions of C60 and C70 fullerenes with crystalline surfaces in ion and laser beam experiments. After his graduate studies, he spent time as a post doc researcher at the Chemistry Department at the Argonne National Laboratory working on sputtered metal cluster experiments with Secondary Neutral Mass Spectrometry with laser post ionization.

He has published over 130 articles and conference papers including first author articles in Physical Review Letters and Science and holds 79 granted patents in the fields of plasma and ion beam sources, plasma etching, Atomic Layer Etching, CVD, reactor design, and diagnostics.