Interconnect Scaling – Implications & Solutions for RC Delay
Growing demand for high performance integrated circuits (ICs) has led to aggressive shrinking of devices. Interconnect speed is rapidly becoming a performance bottleneck. Longer wires, coupled with smaller and more-closely packed interconnects, are leading to a continuous increase in resistance and capacitance, forcing a longer RC interconnect delay.
Meeting the interconnect RC challenge requires innovations on the dielectric, barrier/seed, plating and post-capping processes. This presentation will review the advancements in interconnect metallization such as the use of selective deposition to minimize the high resistance barrier layers at the via interface, process and materials innovations for the scaling of liner films and the reflow-based gap fill schemes to achieve void-free gap fill. Approaches for alternate conductors with higher mean-free path and electromigration resistance will also be benchmarked against the copper interconnects.