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Interconnect Scaling – Implications & Solutions for RC Delay

4:20 pm - 4:40 pm

Growing demand for high performance integrated circuits (ICs) has led to aggressive shrinking of devices. Interconnect speed is rapidly becoming a performance bottleneck. Longer wires, coupled with smaller and more-closely packed interconnects, are leading to a continuous increase in resistance and capacitance, forcing a longer RC interconnect delay.

Meeting the interconnect RC challenge requires innovations on the dielectric, barrier/seed, plating and post-capping processes. This presentation will review the advancements in interconnect metallization such as the use of selective deposition to minimize the high resistance barrier layers at the via interface, process and materials innovations for the scaling of liner films and the reflow-based gap fill schemes to achieve void-free gap fill. Approaches for alternate conductors with higher mean-free path and electromigration resistance will also be benchmarked against the copper interconnects.


K Moraes

Kevin Moraes

Vice President, Metal Deposition Products, Applied Materials

Kevin Moraes is vice president of Global Product Management in the Metal Deposition Products (MDP) division at Applied Materials, Inc. He is responsible for strengthening Applied’s leadership position in metals and PVD deposition, as well as extending the product roadmaps for ALD/CVD and PVD and metal deposition applications. 

Under his direction, the MDP group has strengthened its leadership in its core semiconductor product segments, while developing products for new applications that have significantly grown the business.

Dr. Moraes has published 15 papers and has been awarded 9 patents. He received his Ph.D. in materials science and engineering from Rensselaer Polytechnic Institute, and a bachelor’s degree in chemical engineering from Annamalai University. He also holds an MBA from the Hass School of Business at the University of California, Berkeley.