Skip to main content

Extending Memory and Logic Roadmaps with New Materials and Processes (invited)

1:00 pm - 1:30 pm

While lateral scaling of semiconductor devices traditionally has been the strongest lever to decrease cost per bit or cost per function it is now more and more complemented by exploiting the 3rd dimension in new architectures, such as in FinFET, VNAND and high bandwidth stacked DRAM. Combined lateral and vertical scaling has resulted in an exponential introduction of new materials in the industry, and improved deposition processes. This trend is expected to continue at least for the next decade, but will require a more efficient innovation model with early roadmap alignment to enable quicker down selection of options and reduction of risk.

This presentation will first highlight the key material, process, and architecture changes in the past 10 years, and how they enabled next generation memory and logic device manufacturing. Second, our vision for the next 10 years of exponential changes will be presented.



Ivo J. Raaijmakers

CTO and Corporate VP of R&D, ASM International

Dr. Raaijmakers is currently Chief Technology Officer and Corporate VP of R&D of ASM International NV (“ASM”).

He started his career in 1982 at the Philips Research Labs in the Netherlands. He moved to the USA in 1988, where he held various positions in the area of semiconductor technology development and R&D management at Philips, Novellus and Applied Materials. Dr. Raaijmakers joined ASM in 1996 in its ASM America subsidiary, and was appointed CTO in 1999, based out of ASM’s headquarter back in the Netherlands.

Dr. Raaijmakers has authored over 50 technical publications, has been invited as a speaker to many conferences, and is an inventor on over 100 issued US patents. He holds M.Sc. (“Ir”) (1982) and Ph.D. (1988) degrees in Physics from “Eindhoven University of Technology” (the Netherlands), specializing in Plasma Physics and Materials Science.