Extending Memory and Logic Roadmaps with New Materials and Processes (invited)
While lateral scaling of semiconductor devices traditionally has been the strongest lever to decrease cost per bit or cost per function it is now more and more complemented by exploiting the 3rd dimension in new architectures, such as in FinFET, VNAND and high bandwidth stacked DRAM. Combined lateral and vertical scaling has resulted in an exponential introduction of new materials in the industry, and improved deposition processes. This trend is expected to continue at least for the next decade, but will require a more efficient innovation model with early roadmap alignment to enable quicker down selection of options and reduction of risk.
This presentation will first highlight the key material, process, and architecture changes in the past 10 years, and how they enabled next generation memory and logic device manufacturing. Second, our vision for the next 10 years of exponential changes will be presented.