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Metallization Challenges in 3D NAND (invited)

3:00 pm - 3:40 pm

As 2D planar NAND flash memory scaling became increasingly difficult and cost-prohibitive, 3D NAND architecture emerged as a viable alternative. Thin film deposition in complex geometries and Reactive Ion Etching of multilayer stacks has been pivotal in enabling high yield, low cost 3D NAND production. Continued development for future nodes will require revolutionary approaches due to increased loading densities and cost/bit density requirements. This talk discusses the challenges, production-worthy solutions and future directions in a gate-last approach for 3D NAND metallization.

Due to its thermal stability and excellent electric conductivity at small dimensions, tungsten (W) is widely used for both front-end and back-end metallization in the semiconductor industry. In Charge Trap 3D NAND, W control gates or Word Lines (WL) are formed by a replacement process. However, uniform deposition of barrier layers and nucleation films and void-free gap-fill is not a trivial problem in complex geometries and aspect ratios that routinely exceed 50:1. Meanwhile, 3D NAND extendibility requires W-WL thickness reduction so that total stacked pairs or memory layers can keep increasing over future technology nodes, while meeting acceptable levels of resistance. This makes it even more difficult for gap-filling in sideways recessed 3D fins with shrinking dimensions. In addition, severe wafer warp associated with the increased volume of W, imposes limitations on the number of 3D layers that can be fabricated. Moreover, residual fluorine in the WLs from the WF6 precursor diffuses into inner dielectrics and creates reliability problems -making WL metallization a very key technology that determines 3D NAND scaling.

In this talk, we will review the metallization challenges faced in recent 3D NAND nodes, lessons learnt and the upcoming challenges as we continue 3D NAND scaling for the many years to come. This talk will discuss some of the promising technologies for lowering WL resistance, controlling fluorine content and stress management that include: ALD deposition, fluorine-free barriers/films, and touch upon alternative metals for future generations.



Raghuveer Makala

Raghuveer Makala

Director,Process Engineering, Western Digital

Dr. Raghuveer Makala is Process Engineering Director of Advanced Module Development Group at Western Digital, Milpitas (California) leading Research & Development efforts on Thin Films to enable 3D NAND Flash Memory and extend scaling for future nodes. His team’s recent focus has been on developing 64 Layer and 96 Layer 3D NAND in addition to working on research efforts for emerging memories. Dr. Makala has been with SanDisk (now Western Digital) for the last 11+ years and has worked on multiple high value process engineering problems starting from R&D phase to eventual deployment in mass production.

Prior to SanDisk, Dr. Makala worked at Novellus Systems (now Lam Research) with focus on ALD and CVD of barriers and metal films. Dr. Makala obtained his PhD from Rensselaer Polytechnic Institute (2006) located at Troy, New York, USA and MS from NC State University (2002) located at Raleigh, North Carolina, USA − both in Materials Science & Engineering. During his PhD, he also received the MRS Gold Award from Materials Research Society (MRS), in honor of his academic and scientific research achievements.

His research efforts have so far resulted in 100+ US patents with several more pending and 35+ published papers and conference presentations.