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SAQP Pitch Walking Improvement Path Finding by Simulation

오후 5:10 - 오후 5:30

Spacer masks fabricated by SAQP have a slanted rounded shape with the higher side facing the original sacrificial pattern (mandrel) and the lower side adjacent to the empty space (trench). This asymmetric shape results in different local etch rates in the trench and mandrel region (a.k.a. pitch walking) which can have various negative effects on downstream processes. Pitch walking can be corrected by adjusting spacer size and shape through ALD thickness modifications. Unfortunately, these adjustments are unique to each mask shape and size. Changes to spacer size and shape must be verified each time a stack thickness or pattern size/layout adjustment is made. This greatly increases development time and costs, since experimental wafers must be manufactured to verify the effect of any ALD thickness variation on pitch walking. In this paper, we demonstrate an accelerated methodology to correct pitch walking using virtual process modeling.

In this study, we have created a virtual process model of an FEOL FinFET SAQP process flow with an initial 128 nm pitch and a targeted post-SAQP pitch of 32 nm. The first and second ALD thicknesses of the SAQP flow are selected through a Monte Carlo distribution to have values between 14 to 20 nm. Anisotropic etch processes, such as spacer etch back or mandrel etching, are constant throughout all Monte Carlo runs. Anisotropic etch profiles, such as selectivity, sputter angles, and sidewall bowing are inferred from SEM images of samples etched from a particular tool. The degree of pitch walking is measured by the standard deviation of 4 consecutive fin CDs, as well as spacing in-between, after the entire SAQP process flow.

To determine the optimal ALD thicknesses to minimize pitch walking, we perform a Monte Carlo simulation within our process model by combining fixed etch process values and variable ALD thicknesses. For a particular SAQP flow, we are able to identify 2 ALD thickness values that result in excellent fin and spacer CD variation of less than 0.5 nm. The simulation method is valid for any size, shape of stack thickness, or pattern size, as long as the etch process tools are validated in the model. Adapting this simulation methodology to different etch tools simply requires entering the etch profile of the new tool into the virtual process model. In addition, a Process Window Optimization workflow can be used to understand and identify the ranges of input parameters (i.e. the process window) needed to achieve pitch walking performance goals and optimize product yield. The virtual process modeling technique used in this study can substantially reduce pitch walking during SAQP process development, in a highly time and cost-effective manner.

Speaker

Timothy Yang

Timothy Yang

Software Engineer, Lam Research

Timothy Yang, Ph.D. has been working as a software engineer at Lam Research since August 2018 focused on training and technical support for Semulator3D, a process and integration simulation software used by major semiconductor fabs. Throughout the work, Tim is familiar with the integration and process flow for 3DNAND, DRAM, and has substantial skill in python and C++ programming for this application. 


Prior to joining Lam Research, Tim worked as a process engineer at Tokyo Electron where he developed etch processes for front end of line applications and multi-patterning techniques including SADP and SAQP.

Tim received a bachelor’s degree in Physics from the University of California Los Angeles, and a Ph.D. in Material Science from Tohoku University in Sendai, Miyagi Prefecture, Japan. Tim also has a high interest in new and emerging non-volatile memory technologies, including 3DXpoint, ReRAM and MRAM.