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[Keynote]Augmenting Design & Metrology Reliability through the Application of Focused Ion Beam (FIB) Circuit Prototyping Prior to a Photomask Modification (invited)

오전 10:10 - 오전 10:40

Steve Herschbein, Principal Member of the Technical Staff, GLOBALFOUNDRIES

Microchip Design Manuals attempt to assemble all of the theoretical and experimental knowledge related to semiconductor fabrication process tolerances for a technology node into a unified package. If a new product circuit design is correct and the physical layout lies within the documented specification limits of these guidelines, the end product should function as intended. In-line metrology and inspections feed data into Statistical Process Controls, which regulate the manufacturing line. These statistical process controls work to ensure that all variances of the processes are understood and also serve to automate process centering. These controls ensure that the actual output of the process match the desired characteristics in the Design Manual. It is routine to track a large number of parameters including, but not limited to, critical dimensions and layer overlay alignment. These specific measurable characteristics directly impact transistor and transmission line performance. A well-designed specification, coupled with advanced statistical process controls, stands the best chance of ultimately delivering total chip functionality and reliable product for the end customer application.

Modern processes benefit from continuously improving predictive modeling and ever tightening manufacturing controls. As a result, recent nodes more closely match the Design Manual predictions and rarely exhibit the end-product performance differentials and across-wafer uniformity problems observed in the past.

Wafer final test on the first fabrication runs of a new product provide a solid indicator of hard failures and overall functionality. Comprehensive testing and characterization, however, is best performed on finished modules where the impact of full pin count and chip-package interactions may also become evident. Using die serialization, a further in-depth analysis of wafer location versus module performance can also be checked.

If a die location sensitivity was observed on some prior generation products, Shmoo Plotting of various parameters was often useful to gain an understanding of certain classes of soft fails (temperature, timing, or voltage operating range). At times, some of these sensitivities were traced to a combination of several process parameters which individually were all within specification, but when combined highlighted an area of design marginality. This might lead to a tightening or recentering of an individual measured manufacturing parameter. In other cases, the best solution was to invoke a localized circuit design or layout optimization at the product level.

The full implications of modifying performance via a circuit design change might not be completely apparent until masks have been printed, wafers processed, and product delivery impacted. Just the cost to product a leading edge photomask can exceed $100,000 USD. The high cost, both in time and capital coupled with an uncertain outcome, lent credibility to applying rapid prototyping as a means of validation. The technique known as Focused Ion Beam (FIB) chip circuitry modification has been used at GLOBALFOUNDRIES for fast validation on a number of proposed design optimizations prior to execution.

The FIB editing tool is a ‘direct write’ system that can be used to selectively reconfigure a chip’s internal functions. A precisely tuned and placed ion beam in conjunction with etch and deposition process gases are used to selectively uncover internal circuitry and rewrite the copper wiring pattern. Transistors can be removed or modified to change their operating characteristics, and simple elements like resistors or capacitors added. Work can be performed on wafer segments for test probe evaluation, or on finished modules for more extensive testing and system verification. For many basic revisions, the FIB edited product functions essentially the same as the new fabricated product, except the results can be obtained weeks or even months earlier. The edited chip is the very essence of handcrafted prototyping. Evaluating proposed revisions first through FIB modification has become an important part of the release process at GLOBALFOUNDRIES and other companies. A few examples of the FIB mask change verification process will be shown.

Speaker

MI_Steven B. Herschbein

Steve Herschbein

Principal Member of the Technical Staff, GlobalFoundries

Steve is the FIB Chip Circuit Edit team leader at GLOBALFOUNDRIES, and has been heavily involved in FIB tooling, applications & development for over 25 years. In addition to Lab oriented activity, Steve was an early industry player in the effort to bring FIB technology into the 300mm Fab line for defect review, process monitoring and metrology applications.

Previous employers include IBM Microelectronics, Harris Semiconductor, MOSTEK and Fairchild Semiconductor in various Lab and Fab roles, dating back to 1978. Steve holds a BS in Electrical Engineering from Clarkson University in New York.