Advanced Plasma Etch Schemes for EUV Patterning (invited)
With the continuous scaling down of memory and logic technologies necessary to improve device performances and lower power consumption, new requirements and more challenges appear with every new node. A precise control of critical dimensions at the sub-nanometer level is essential to ensure a reliable fabrication process with sufficient yield. EUV lithography allows a significant gain in pattern dimension and process flow simplicity, but also brings its own share of difficulties such as lower PR thickness, higher roughness and higher defectivity. To tackle those challenges, EUV patterning involves the development of innovative plasma etch processes in close collaboration with stack, lithography and process flow co-optimizations.
In this presentation, we discuss advancements and limitations of single EUV patterning processes and multiple patterning schemes such as SA-LELE for N5 node and below.