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The Enhancement of Logic SCAN Diagnostics Using Machine Learning Technique for the Fast Yield Ramp Up

오후 4:20 - 오후 4:50

 The yield ramp-up is increasing challenges for the advanced Logic technology (5/7/10nm) because there are a lot of new factors. For example, new light source, new materials and new unit process, etc. Other challenges are how fast we can identify the systematic failure. Cycle time to produce the wafer is continuously increasing because the design and process is more complex for these tech nodes. We could loss so much time to find the root cause during several iteration without relevant methodology.

 The EDS testing and SCAN diagnostics is very important for this purpose. The most of wafers are tested after fab-out and then we can extract key factors to identify the systematic failures from these testing data. But the traditional methodology using these data still have some limitation for moving it into the physical failure mechanism. Because scan diagnostics are inherently noisy, the results often require expert knowledge to manually select the location that has the highest likelihood of being correct. So, the Volume Scan Diagnostics Analysis (VSDA) has become a mainstream methodology that supplements traditional yield learning.

 In this paper, we introduce the Failure Mechanism Analysis (FMA) with the technique of Machine Learning in a yield analysis system that can empirically estimate sources of yield loss using physical diagnostic information.

abstract image(JS Park)

Fig. 1. Failure Mechanism analysis using Volume diagnostics with Yield explorer® [1]

Ref. 1 Chris Schuermyer et al., 30th SEMI Advanced Semiconductor Manufacturing Conf, 2019

Speaker

Jeongsu Park

Jeongsu Park

Staff Engineer, Silicon Engineering Group, Synopsys

Jeongsu Park is a Staff Engineer(부장), Manufacturing Yield Management part, Silicon Engineering group at Synopsys Korea.

Jeongsu Park has been provided a technical supporting and consulting for the Yield Analysis and Failure Analysis at Synopsys, Korea for over 4 years. His expertise includes from the new analysis methodology of Wafer level Testing (ATE), DFT (Design-For-Testing), DFM (Design-For-Manufacturing) for the yield improvement of Fabless and Foundry companies.

Prior to joining the Synopsys, Jeongsu Park worked on process integration and yield analysis for the 20 ~ 65nm Logic process in Samsung S.LSI Foundry biz over 5 years. Notable contributions include the stress engineering, high-k metal gate architecture, and Cu metallization. He had a various experience with Tier 1 fabless customers.

He worked on the process development for the CMOS Image Sensor at Dongbu HiTek before joining Samsung over 4 years. Mainly focused on the characterization of vertical photodiode structure with several epitaxial layers and the process integration of photodiode and BEOL process.

He earned a M.S. in Material Science and Engineering in 2002 from Ajou University.