The Enhancement of Logic SCAN Diagnostics Using Machine Learning Technique for the Fast Yield Ramp Up
The yield ramp-up is increasing challenges for the advanced Logic technology (5/7/10nm) because there are a lot of new factors. For example, new light source, new materials and new unit process, etc. Other challenges are how fast we can identify the systematic failure. Cycle time to produce the wafer is continuously increasing because the design and process is more complex for these tech nodes. We could loss so much time to find the root cause during several iteration without relevant methodology.
The EDS testing and SCAN diagnostics is very important for this purpose. The most of wafers are tested after fab-out and then we can extract key factors to identify the systematic failures from these testing data. But the traditional methodology using these data still have some limitation for moving it into the physical failure mechanism. Because scan diagnostics are inherently noisy, the results often require expert knowledge to manually select the location that has the highest likelihood of being correct. So, the Volume Scan Diagnostics Analysis (VSDA) has become a mainstream methodology that supplements traditional yield learning.
In this paper, we introduce the Failure Mechanism Analysis (FMA) with the technique of Machine Learning in a yield analysis system that can empirically estimate sources of yield loss using physical diagnostic information.
Fig. 1. Failure Mechanism analysis using Volume diagnostics with Yield explorer® 
Ref. 1 Chris Schuermyer et al., 30th SEMI Advanced Semiconductor Manufacturing Conf, 2019