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Role and Responsibility of CMP Process in Recent IC Technology

오전 9:00 - 오전 10:15

반도체 소자의 고속화 고집적화에 따라 다층배선구조에 있어서 배선층수의 증가와 패턴의 미세화에 대한 요구가 여전히 높다.

CMP (Chemical Mechanical Planarization) 미세패턴의 광역평탄화를 실현하기 위해 도입되었으며, device 공정에 폭넓게 사용되고 있다특히 새로운 design module 공정 형성에 있어서의 필요성이 나날이 커지고 있다구조적 CMP 요구와 더불어 또한 새로운 물질의 도입에 따른 CMP 적용에 대한 이해가 필요한 시점이다 강의에서는 CMP 기본 개념과 필수 구성요소를 장비와 재료 측면에서 살펴보고최근의 device 어떻게 사용 전개되고 있는지에 대해 다루고자 한다.

Speaker

JI CHUL YANG

Ji Chul Yang

Research Fellow / Vice President, SK hynix

Dr. Ji Chul Yang is Fellow/Vice President at SK hynix Semiconductor in South Korea. Since he joined SK hynix in 2017, he is now responsible for Cleaning&CMP innovation team in Manufacturing Division. Prior to SK hynix, he was CMP team leader and CMP Representative of Future Technology Roadmap Team at GLOBALFOUNDRIES U.S. He was also engaged in developing 14nm & 7 nm logic CMP process as technical leader. Prior to his time with Globalfoundries, Dr. Yang was CMP Project Leader in Line 16, SAMSUNG Memory Division in South Korea. He has experiences throughout Memory (NAND and DRAM) and Logic Foundries Device over 20 years in semiconductor CMP field. He was invited talker for ICPT2018, ICPT2014, ICPT2010, 60th KCMPUGM, ECS2016, SEMICONWEST-CMP2016 and STS2017. Dr. Yang has a Ph.D degree in Electronics Engineering from SUNGKYUNKWAN University, South Korea, Master’s degree in Mechanical Engineering from YONSEI University. He has authored more than 40 technical publications and conference presentations with semiconductor items.