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SEMI is soliciting presentations from authors around the world for annual SEMI Technology Symposium (STS) 2020, which will be held in conjunction with SEMICON Korea 2020 exhibition. Individuals are encouraged to submit original presentations related to any of the following categories.

Session 1. Advanced Lithography

  • Extreme Ultraviolet Lithography including Sources and High NA
  • Mask Process, Blank, Pellicle and Infrastructure
  • Modeling and Simulation (Stochastic, Mask 3D Effect, and others)
  • Directed Self Assembly and its Application
  • Alternative Lithography (Nano-Imprint, Non-Optical and others)
  • Various Multiple Patterning Techniques
  • Patterning Materials and Processes
  • OPC and Design Process Technology Co-Optimization for Manufacturability
  • Advanced Metrology Technology for Wafer and Mask
  • Application of Lithography to Semiconductor IC and Nanotechnology

Session 2. Advanced Materials & Process Technology

  • Gapfill Materials and Process
  • Interconnection Processes (Metallic and Optical Interconnects)
  • Dielectric Processes for Gate, Capacitor, Interconnect, and Passivation
  • Doping & Heat Treatment Process (I2p, Plasma Doping, GILD, SADS, RTP, Furnace, Damage Control)
  • Area Selective Deposition
  • SOI Materials & Processes (Wafer and Device Manufacturing)
  • Materials and Processes for Non Volatile Memory Devices
  • Materials and Process for Atomic-scale Deposition
  • Process for Low-dimensional Devices (Quantum Dots and Nano-wires)
  • 2D Materials Technology (Graphene, Sulfide, and etc.)
  • Materials for Flexible/ Plastic Electronics
  • Materials and Process for Beyond Moore

Session 3. Device Technology

  • BCD (Bipolar-CMOS-DMOS)/ NVM (Non-Volatile Memory)/ Analog/ MEMS
  • A.I.-friendly Device Technology
  • SoC Technology
  • Advanced CMOS Technology
  • Advanced Memory Technology
  • SOI Devices
  • RF Devices
  • Nano-scale Devices
  • Thin Film Devices
  • Interconnection Technology
  • Advanced Junction/Doping Technology
  • Process/Device/Interconnection Modeling
  • Device/Interconnection Reliability
  • Device Technology for Mobile/ Automotive Application
  • Emerging Devices- Phase Transitions, Negative Capacitance, Negative Resistance, Spintronics
  • Low-dimensional Devices- 2D Materials, Nanowires

Session 4. Plasma Science and Etching Technology

  • Dry Etching of EUV Mask Pattern (T2T Margin, New Materials, Defect & etc)
  • EUV Multi Patterning Technologies (DPT, QPT, n(LE) & etc) 
  • Next Generation Etching Technology (In-situ ALD/ALE, Ultra-low Temp. Etch, Radical Etch, etc.)
  • High Selective Etch Technique
  • Atomic Layer Etching (ALE) and Low Damage Etching (LDE)
  • Etch Technologies related to FEOL (FNFET and GAA etc.) and BEOL (SAC & small CNT, Low-k etc.)
  • Ultra-fine HARC & HART Etch Technology
  • Tool to Tool Matching (TTTM) Technologies
  • Plasma & Process Diagnostics, Sensors, and Control
  • Simulation and Modeling for Plasma Source and Process 
  • Innovative Approaches to Atomic Layer Material Removal
  • Control of Extreme Edge Uniformity for <10nm Patterning
  • Fine APC (Automatic Process Control) Technology, and Virtual Monitoring Technology
  • Advanced Plasma Based Dry Cleaning Process
  • 3D Etch Technologies for VNAND, 3D X-point, FinFET, Nano Wire, TSV and etc.
  • New & Novel Material Etch for MRAM, PRAM, ReRAM and etc.

Session 5. Contamination-free Manufacturing and CMP Technology

  • Advanced Wet/Dry Surface Preparation in FEOL/BEOL
  • Particle Removal Mechanism & Technology
  • Micro-, Nano-contamination Control
  • Damage/Loss Free Nano Particle Removal
  • Yield Enhancement Technology
  • Environmentally Benign Manufacturing/PFC Emission Reduction
  • Advanced Wet/ Dry Cleaning for 3D Structure and New Materials
  • Interface Control in Cleaning
  • Drying & Leaning Free Technology
  • Advanced CMP Process Control
  • Advances in CMP Metrology and Equipment
  • CMP Consumables: Slurry, Pad, Conditioner, and Filter
  • Machine Learning in CMP
  • Challenge for Future CMP & New Technology (Equipment & Material)
  • Scratch Reduction/Mechanism
  • CMP Modeling and Simulation
  • Post CMP Cleaning
  • Robust CMP Process for Pattern Loading Effect Minimize
  • Alternative CMP Technologies
  • CMP for New Materials and MEMS

Session 6. Electropackage System and Interconnect Product

  • Fan-Out Wafer Level Packaging
  • Fan-Out Panel Level Packaging
  • SiP/ FOWLP SiP/ FOPLP SiP
  • Double Sides BGA (Double Sided Assembly, Double Sided Mold)
  • Warpage Technology (WLFO Warpage, Substrate Warpage, POP Warpage)
  • Delamination Prevention
  • Cu Interconnection (Cu Bump, Cu Wire, Cu Clip, etc.) Reliability
  • Various MEMS/ Sensor Fusion Packaging Technology
  • Package Level EMI Shielding Technology
  • 5G Antenna Module Packaging
  • Packaging/ Design Simulation Technology
  • Substrate Structure Technology (Embedded PCB, SLP, Coreless Thin, Molded Leadframe and etc.)
  • Substrate Material Technology (Dielectric Material for 5G and etc.)
  • Packaging Process Automatic Inspection System (AOI, X-ray and etc.)

Prospective authors are requested to submit an abstract of 500 words and a 100 words biography by September 30, 2019 indicating the category for which the abstract is being submitted. Presentations are to be non-commercial in that they will focus on the technical merits rather than on individual company’s product benefits. Selected speakers will be notified by October 31, 2019. A final presentation file will be required by January 31, 2020.

Accepted presentations are subject to co-copyright with SEMI, who reserves the right to republish, re-sell and display submitted material in whole or in part.

SEMI is soliciting presentations from authors around the world for annual SEMI Technology Symposium (STS) 2020, which will be held in conjunction with SEMICON Korea 2020 exhibition. Individuals are encouraged to submit original presentations related to any of the following categories.

Session 1. Advanced Lithography

  • Extreme Ultraviolet Lithography including Sources and High NA
  • Mask Process, Blank, Pellicle and Infrastructure
  • Modeling and Simulation (Stochastic, Mask 3D Effect, and others)
  • Directed Self Assembly and its Application
  • Alternative Lithography (Nano-Imprint, Non-Optical and others)
  • Various Multiple Patterning Techniques
  • Patterning Materials and Processes
  • OPC and Design Process Technology Co-Optimization for Manufacturability
  • Advanced Metrology Technology for Wafer and Mask
  • Application of Lithography to Semiconductor IC and Nanotechnology

Session 2. Advanced Materials & Process Technology

  • Gapfill Materials and Process
  • Interconnection Processes (Metallic and Optical Interconnects)
  • Dielectric Processes for Gate, Capacitor, Interconnect, and Passivation
  • Doping & Heat Treatment Process (I2p, Plasma Doping, GILD, SADS, RTP, Furnace, Damage Control)
  • Area Selective Deposition
  • SOI Materials & Processes (Wafer and Device Manufacturing)
  • Materials and Processes for Non Volatile Memory Devices
  • Materials and Process for Atomic-scale Deposition
  • Process for Low-dimensional Devices (Quantum Dots and Nano-wires)
  • 2D Materials Technology (Graphene, Sulfide, and etc.)
  • Materials for Flexible/ Plastic Electronics
  • Materials and Process for Beyond Moore

Session 3. Device Technology

  • BCD (Bipolar-CMOS-DMOS)/ NVM (Non-Volatile Memory)/ Analog/ MEMS
  • A.I.-friendly Device Technology
  • SoC Technology
  • Advanced CMOS Technology
  • Advanced Memory Technology
  • SOI Devices
  • RF Devices
  • Nano-scale Devices
  • Thin Film Devices
  • Interconnection Technology
  • Advanced Junction/Doping Technology
  • Process/Device/Interconnection Modeling
  • Device/Interconnection Reliability
  • Device Technology for Mobile/ Automotive Application
  • Emerging Devices- Phase Transitions, Negative Capacitance, Negative Resistance, Spintronics
  • Low-dimensional Devices- 2D Materials, Nanowires

Session 4. Plasma Science and Etching Technology

  • Dry Etching of EUV Mask Pattern (T2T Margin, New Materials, Defect & etc)
  • EUV Multi Patterning Technologies (DPT, QPT, n(LE) & etc) 
  • Next Generation Etching Technology (In-situ ALD/ALE, Ultra-low Temp. Etch, Radical Etch, etc.)
  • High Selective Etch Technique
  • Atomic Layer Etching (ALE) and Low Damage Etching (LDE)
  • Etch Technologies related to FEOL (FNFET and GAA etc.) and BEOL (SAC & small CNT, Low-k etc.)
  • Ultra-fine HARC & HART Etch Technology
  • Tool to Tool Matching (TTTM) Technologies
  • Plasma & Process Diagnostics, Sensors, and Control
  • Simulation and Modeling for Plasma Source and Process 
  • Innovative Approaches to Atomic Layer Material Removal
  • Control of Extreme Edge Uniformity for <10nm Patterning
  • Fine APC (Automatic Process Control) Technology, and Virtual Monitoring Technology
  • Advanced Plasma Based Dry Cleaning Process
  • 3D Etch Technologies for VNAND, 3D X-point, FinFET, Nano Wire, TSV and etc.
  • New & Novel Material Etch for MRAM, PRAM, ReRAM and etc.

Session 5. Contamination-free Manufacturing and CMP Technology

  • Advanced Wet/Dry Surface Preparation in FEOL/BEOL
  • Particle Removal Mechanism & Technology
  • Micro-, Nano-contamination Control
  • Damage/Loss Free Nano Particle Removal
  • Yield Enhancement Technology
  • Environmentally Benign Manufacturing/PFC Emission Reduction
  • Advanced Wet/ Dry Cleaning for 3D Structure and New Materials
  • Interface Control in Cleaning
  • Drying & Leaning Free Technology
  • Advanced CMP Process Control
  • Advances in CMP Metrology and Equipment
  • CMP Consumables: Slurry, Pad, Conditioner, and Filter
  • Machine Learning in CMP
  • Challenge for Future CMP & New Technology (Equipment & Material)
  • Scratch Reduction/Mechanism
  • CMP Modeling and Simulation
  • Post CMP Cleaning
  • Robust CMP Process for Pattern Loading Effect Minimize
  • Alternative CMP Technologies
  • CMP for New Materials and MEMS

Session 6. Electropackage System and Interconnect Product

  • Fan-Out Wafer Level Packaging
  • Fan-Out Panel Level Packaging
  • SiP/ FOWLP SiP/ FOPLP SiP
  • Double Sides BGA (Double Sided Assembly, Double Sided Mold)
  • Warpage Technology (WLFO Warpage, Substrate Warpage, POP Warpage)
  • Delamination Prevention
  • Cu Interconnection (Cu Bump, Cu Wire, Cu Clip, etc.) Reliability
  • Various MEMS/ Sensor Fusion Packaging Technology
  • Package Level EMI Shielding Technology
  • 5G Antenna Module Packaging
  • Packaging/ Design Simulation Technology
  • Substrate Structure Technology (Embedded PCB, SLP, Coreless Thin, Molded Leadframe and etc.)
  • Substrate Material Technology (Dielectric Material for 5G and etc.)
  • Packaging Process Automatic Inspection System (AOI, X-ray and etc.)

Prospective authors are requested to submit an abstract of 500 words and a 100 words biography by September 30, 2019 indicating the category for which the abstract is being submitted. Presentations are to be non-commercial in that they will focus on the technical merits rather than on individual company’s product benefits. Selected speakers will be notified by October 31, 2019. A final presentation file will be required by January 31, 2020.

Accepted presentations are subject to co-copyright with SEMI, who reserves the right to republish, re-sell and display submitted material in whole or in part.

Submission is closed. Thank you for your interest in the STS.

Program team