Giuseppe Garcea

Giuseppe Garcea has more than 20 years of experience in semiconductor. He holds a PhD from TU Delft the Netherlands. He has been working for Magma design Automation (currently Synopsys) focusing on Clock tree synthesis (CTS). He joined Compaan working on heterogeneous computing. In 2012, he was hired at Intel, where he served as a logical designer engineer and then as engineering manager of the logical design and verification. He participated to the tape out of Skylake, Broxton on 14nm and IceLake and TigerLake on 10nm working on camera subsystem blocks. He moved then to the 5G modem business unit leading a team of LD and verification and PD, working specifically on DSP and infra blocks for Polaris and XMM8160. After 8 years at Intel, he decided to move to Bitfury as HW R&D Director and from there he was part of the core team founding Axelera AI in July 2021. Within Axelera he contributed in creating from scratch the silicon organization and instrumental to 3 TO in 3 years on 12nm managing Verification, DFT and PD teams and all the external design services. Today as Director of Silicon he is mostly focusing on driving silicon operations.