Gaurav Thareja

Gaurav Thareja is Head of Logic and Memory Process Integration in the Metals Deposition Products division of the Semiconductor Products Group at Applied Materials, Santa Clara, USA. With a prolific career, he has made significant contributions to semiconductor device processes and materials technology. He is a recognized inventor, holding 40+ US patents, and having authored more than 30 publications and many invited talks. He received PhD in Electrical Engineering from Stanford University and has over 15 years of experience in the semiconductor industry, previously as founding team and COO of an AI startup, Process integration lead for High performance logic for 7/3/2nm nodes at Intel Process Technology Development, Design engineer for transistor reliability CAD at Texas Instruments, and internship for ROM circuit design at ST Microelectronics.